Contiki 3.x
MKL25Z4_features.h
1 /*
2 ** ###################################################################
3 ** Version: rev. 2.10, 2015-05-27
4 ** Build: b150715
5 **
6 ** Abstract:
7 ** Chip specific module features.
8 **
9 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
10 ** All rights reserved.
11 **
12 ** Redistribution and use in source and binary forms, with or without modification,
13 ** are permitted provided that the following conditions are met:
14 **
15 ** o Redistributions of source code must retain the above copyright notice, this list
16 ** of conditions and the following disclaimer.
17 **
18 ** o Redistributions in binary form must reproduce the above copyright notice, this
19 ** list of conditions and the following disclaimer in the documentation and/or
20 ** other materials provided with the distribution.
21 **
22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
23 ** contributors may be used to endorse or promote products derived from this
24 ** software without specific prior written permission.
25 **
26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 **
37 ** http: www.freescale.com
38 ** mail: support@freescale.com
39 **
40 ** Revisions:
41 ** - rev. 1.0 (2012-06-13)
42 ** Initial version.
43 ** - rev. 1.1 (2012-06-21)
44 ** Update according to reference manual rev. 1.
45 ** - rev. 1.2 (2012-08-01)
46 ** Device type UARTLP changed to UART0.
47 ** - rev. 1.3 (2012-10-04)
48 ** Update according to reference manual rev. 3.
49 ** - rev. 1.4 (2012-11-22)
50 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
51 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
52 ** - rev. 2.0 (2013-10-29)
53 ** Register accessor macros added to the memory map.
54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
55 ** Startup file for gcc has been updated according to CMSIS 3.2.
56 ** System initialization updated.
57 ** - rev. 2.1 (2014-01-30)
58 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
59 ** - rev. 2.2 (2014-07-16)
60 ** Module access macro module_BASES replaced by module_BASE_PTRS.
61 ** System initialization and startup updated.
62 ** - rev. 2.3 (2014-08-22)
63 ** System initialization updated - default clock config changed.
64 ** - rev. 2.4 (2014-08-28)
65 ** Update of startup files - possibility to override DefaultISR added.
66 ** - rev. 2.5 (2014-10-14)
67 ** Interrupt INT_LPTimer renamed to INT_LPTMR0.
68 ** - rev. 2.6 (2015-01-21)
69 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
70 ** - rev. 2.7 (2015-02-19)
71 ** Renamed interrupt vector LLW to LLWU.
72 ** - rev. 2.8 (2015-05-19)
73 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
74 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
75 ** Added features for PORT.
76 ** - rev. 2.9 (2015-05-25)
77 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
78 ** - rev. 2.10 (2015-05-27)
79 ** Several USB features added.
80 **
81 ** ###################################################################
82 */
83 
84 #if !defined(__FSL_MKL25Z4_FEATURES_H__)
85 #define __FSL_MKL25Z4_FEATURES_H__
86 
87 /* ADC16 module features */
88 
89 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
90 #define FSL_FEATURE_ADC16_HAS_PGA (0)
91 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
92 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
93 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
94 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
95 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
96 #define FSL_FEATURE_ADC16_HAS_DMA (1)
97 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
98 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
99 /* @brief Has FIFO (bit SC4[AFDEP]). */
100 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
101 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
102 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
103 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
104 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
105 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
106 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
107 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
108 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
109 /* @brief Has HW averaging (bit SC3[AVGE]). */
110 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
111 /* @brief Has offset correction (register OFS). */
112 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
113 /* @brief Maximum ADC resolution. */
114 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
115 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
116 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
117 
118 /* CMP module features */
119 
120 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
121 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
122 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
123 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
124 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
125 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
126 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
127 #define FSL_FEATURE_CMP_HAS_DMA (1)
128 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
129 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
130 /* @brief Has DAC Test function in CMP (register DACTEST). */
131 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
132 
133 /* COP module features */
134 
135 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
136 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0)
137 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
138 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (0)
139 /* @brief Has more clock sources like MCGIRC */
140 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0)
141 /* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */
142 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0)
143 
144 /* SOC module features */
145 
146 /* @brief ACMP availability on the SoC. */
147 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
148 /* @brief ADC16 availability on the SoC. */
149 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
150 /* @brief AFE availability on the SoC. */
151 #define FSL_FEATURE_SOC_AFE_COUNT (0)
152 /* @brief AIPS availability on the SoC. */
153 #define FSL_FEATURE_SOC_AIPS_COUNT (0)
154 /* @brief AOI availability on the SoC. */
155 #define FSL_FEATURE_SOC_AOI_COUNT (0)
156 /* @brief AXBS availability on the SoC. */
157 #define FSL_FEATURE_SOC_AXBS_COUNT (0)
158 /* @brief CADC availability on the SoC. */
159 #define FSL_FEATURE_SOC_CADC_COUNT (0)
160 /* @brief FLEXCAN availability on the SoC. */
161 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
162 /* @brief MMCAU availability on the SoC. */
163 #define FSL_FEATURE_SOC_MMCAU_COUNT (0)
164 /* @brief CMP availability on the SoC. */
165 #define FSL_FEATURE_SOC_CMP_COUNT (1)
166 /* @brief CMT availability on the SoC. */
167 #define FSL_FEATURE_SOC_CMT_COUNT (0)
168 /* @brief CNC availability on the SoC. */
169 #define FSL_FEATURE_SOC_CNC_COUNT (0)
170 /* @brief CRC availability on the SoC. */
171 #define FSL_FEATURE_SOC_CRC_COUNT (0)
172 /* @brief DAC availability on the SoC. */
173 #define FSL_FEATURE_SOC_DAC_COUNT (1)
174 /* @brief DCDC availability on the SoC. */
175 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
176 /* @brief DDR availability on the SoC. */
177 #define FSL_FEATURE_SOC_DDR_COUNT (0)
178 /* @brief DMA availability on the SoC. */
179 #define FSL_FEATURE_SOC_DMA_COUNT (1)
180 /* @brief DMAMUX availability on the SoC. */
181 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
182 /* @brief DRY availability on the SoC. */
183 #define FSL_FEATURE_SOC_DRY_COUNT (0)
184 /* @brief DSPI availability on the SoC. */
185 #define FSL_FEATURE_SOC_DSPI_COUNT (0)
186 /* @brief EDMA availability on the SoC. */
187 #define FSL_FEATURE_SOC_EDMA_COUNT (0)
188 /* @brief EMVSIM availability on the SoC. */
189 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
190 /* @brief ENC availability on the SoC. */
191 #define FSL_FEATURE_SOC_ENC_COUNT (0)
192 /* @brief ENET availability on the SoC. */
193 #define FSL_FEATURE_SOC_ENET_COUNT (0)
194 /* @brief EWM availability on the SoC. */
195 #define FSL_FEATURE_SOC_EWM_COUNT (0)
196 /* @brief FB availability on the SoC. */
197 #define FSL_FEATURE_SOC_FB_COUNT (0)
198 /* @brief FGPIO availability on the SoC. */
199 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
200 /* @brief FLEXIO availability on the SoC. */
201 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
202 /* @brief FMC availability on the SoC. */
203 #define FSL_FEATURE_SOC_FMC_COUNT (0)
204 /* @brief FSKDT availability on the SoC. */
205 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
206 /* @brief FTFA availability on the SoC. */
207 #define FSL_FEATURE_SOC_FTFA_COUNT (1)
208 /* @brief FTFE availability on the SoC. */
209 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
210 /* @brief FTFL availability on the SoC. */
211 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
212 /* @brief FTM availability on the SoC. */
213 #define FSL_FEATURE_SOC_FTM_COUNT (0)
214 /* @brief FTMRA availability on the SoC. */
215 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
216 /* @brief FTMRE availability on the SoC. */
217 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
218 /* @brief FTMRH availability on the SoC. */
219 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
220 /* @brief GPIO availability on the SoC. */
221 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
222 /* @brief HSADC availability on the SoC. */
223 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
224 /* @brief I2C availability on the SoC. */
225 #define FSL_FEATURE_SOC_I2C_COUNT (2)
226 /* @brief I2S availability on the SoC. */
227 #define FSL_FEATURE_SOC_I2S_COUNT (0)
228 /* @brief ICS availability on the SoC. */
229 #define FSL_FEATURE_SOC_ICS_COUNT (0)
230 /* @brief IRQ availability on the SoC. */
231 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
232 /* @brief KBI availability on the SoC. */
233 #define FSL_FEATURE_SOC_KBI_COUNT (0)
234 /* @brief SLCD availability on the SoC. */
235 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
236 /* @brief LCDC availability on the SoC. */
237 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
238 /* @brief LDO availability on the SoC. */
239 #define FSL_FEATURE_SOC_LDO_COUNT (0)
240 /* @brief LLWU availability on the SoC. */
241 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
242 /* @brief LMEM availability on the SoC. */
243 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
244 /* @brief LPSCI availability on the SoC. */
245 #define FSL_FEATURE_SOC_LPSCI_COUNT (1)
246 /* @brief LPTMR availability on the SoC. */
247 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
248 /* @brief LPTPM availability on the SoC. */
249 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
250 /* @brief LPUART availability on the SoC. */
251 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
252 /* @brief LTC availability on the SoC. */
253 #define FSL_FEATURE_SOC_LTC_COUNT (0)
254 /* @brief MC availability on the SoC. */
255 #define FSL_FEATURE_SOC_MC_COUNT (0)
256 /* @brief MCG availability on the SoC. */
257 #define FSL_FEATURE_SOC_MCG_COUNT (1)
258 /* @brief MCGLITE availability on the SoC. */
259 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
260 /* @brief MCM availability on the SoC. */
261 #define FSL_FEATURE_SOC_MCM_COUNT (1)
262 /* @brief MMAU availability on the SoC. */
263 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
264 /* @brief MMDVSQ availability on the SoC. */
265 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
266 /* @brief MPU availability on the SoC. */
267 #define FSL_FEATURE_SOC_MPU_COUNT (0)
268 /* @brief MSCAN availability on the SoC. */
269 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
270 /* @brief MTB availability on the SoC. */
271 #define FSL_FEATURE_SOC_MTB_COUNT (1)
272 /* @brief MTBDWT availability on the SoC. */
273 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
274 /* @brief NFC availability on the SoC. */
275 #define FSL_FEATURE_SOC_NFC_COUNT (0)
276 /* @brief OPAMP availability on the SoC. */
277 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
278 /* @brief OSC availability on the SoC. */
279 #define FSL_FEATURE_SOC_OSC_COUNT (1)
280 /* @brief OTFAD availability on the SoC. */
281 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
282 /* @brief PDB availability on the SoC. */
283 #define FSL_FEATURE_SOC_PDB_COUNT (0)
284 /* @brief PGA availability on the SoC. */
285 #define FSL_FEATURE_SOC_PGA_COUNT (0)
286 /* @brief PIT availability on the SoC. */
287 #define FSL_FEATURE_SOC_PIT_COUNT (1)
288 /* @brief PMC availability on the SoC. */
289 #define FSL_FEATURE_SOC_PMC_COUNT (1)
290 /* @brief PORT availability on the SoC. */
291 #define FSL_FEATURE_SOC_PORT_COUNT (5)
292 /* @brief PWM availability on the SoC. */
293 #define FSL_FEATURE_SOC_PWM_COUNT (0)
294 /* @brief PWT availability on the SoC. */
295 #define FSL_FEATURE_SOC_PWT_COUNT (0)
296 /* @brief QuadSPIO availability on the SoC. */
297 #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
298 /* @brief RCM availability on the SoC. */
299 #define FSL_FEATURE_SOC_RCM_COUNT (1)
300 /* @brief RFSYS availability on the SoC. */
301 #define FSL_FEATURE_SOC_RFSYS_COUNT (0)
302 /* @brief RFVBAT availability on the SoC. */
303 #define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
304 /* @brief RNG availability on the SoC. */
305 #define FSL_FEATURE_SOC_RNG_COUNT (0)
306 /* @brief RNGB availability on the SoC. */
307 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
308 /* @brief ROM availability on the SoC. */
309 #define FSL_FEATURE_SOC_ROM_COUNT (1)
310 /* @brief RSIM availability on the SoC. */
311 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
312 /* @brief RTC availability on the SoC. */
313 #define FSL_FEATURE_SOC_RTC_COUNT (1)
314 /* @brief SCI availability on the SoC. */
315 #define FSL_FEATURE_SOC_SCI_COUNT (0)
316 /* @brief SDHC availability on the SoC. */
317 #define FSL_FEATURE_SOC_SDHC_COUNT (0)
318 /* @brief SDRAM availability on the SoC. */
319 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
320 /* @brief SIM availability on the SoC. */
321 #define FSL_FEATURE_SOC_SIM_COUNT (1)
322 /* @brief SMC availability on the SoC. */
323 #define FSL_FEATURE_SOC_SMC_COUNT (1)
324 /* @brief SPI availability on the SoC. */
325 #define FSL_FEATURE_SOC_SPI_COUNT (2)
326 /* @brief TMR availability on the SoC. */
327 #define FSL_FEATURE_SOC_TMR_COUNT (0)
328 /* @brief TPM availability on the SoC. */
329 #define FSL_FEATURE_SOC_TPM_COUNT (3)
330 /* @brief TRIAMP availability on the SoC. */
331 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
332 /* @brief TRNG availability on the SoC. */
333 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
334 /* @brief TSI availability on the SoC. */
335 #define FSL_FEATURE_SOC_TSI_COUNT (1)
336 /* @brief UART availability on the SoC. */
337 #define FSL_FEATURE_SOC_UART_COUNT (2)
338 /* @brief USB availability on the SoC. */
339 #define FSL_FEATURE_SOC_USB_COUNT (1)
340 /* @brief USBDCD availability on the SoC. */
341 #define FSL_FEATURE_SOC_USBDCD_COUNT (0)
342 /* @brief USBHSDCD availability on the SoC. */
343 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
344 /* @brief USBPHY availability on the SoC. */
345 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
346 /* @brief VREF availability on the SoC. */
347 #define FSL_FEATURE_SOC_VREF_COUNT (0)
348 /* @brief WDOG availability on the SoC. */
349 #define FSL_FEATURE_SOC_WDOG_COUNT (0)
350 /* @brief XBAR availability on the SoC. */
351 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
352 /* @brief XCVR availability on the SoC. */
353 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
354 /* @brief ZLL availability on the SoC. */
355 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
356 
357 /* DAC module features */
358 
359 /* @brief Define the size of hardware buffer */
360 #define FSL_FEATURE_DAC_BUFFER_SIZE (2)
361 /* @brief Define whether the buffer supports watermark event detection or not. */
362 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
363 /* @brief Define whether the buffer supports watermark selection detection or not. */
364 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
365 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
366 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
367 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
368 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
369 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
370 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
371 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
372 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
373 /* @brief Define whether FIFO buffer mode is available or not. */
374 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
375 /* @brief Define whether swing buffer mode is available or not.. */
376 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
377 
378 /* DMA module features */
379 
380 /* @brief Total number of DMA channels on all modules. */
381 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 4)
382 
383 /* DMAMUX module features */
384 
385 /* @brief Number of DMA channels (related to number of register CHCFGn). */
386 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
387 /* @brief Total number of DMA channels on all modules. */
388 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 4)
389 /* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
390 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
391 
392 /* FLASH module features */
393 
394 #if defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z32VLK4)
395  /* @brief Is of type FTFA. */
396  #define FSL_FEATURE_FLASH_IS_FTFA (1)
397  /* @brief Is of type FTFE. */
398  #define FSL_FEATURE_FLASH_IS_FTFE (0)
399  /* @brief Is of type FTFL. */
400  #define FSL_FEATURE_FLASH_IS_FTFL (0)
401  /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
402  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
403  /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
404  #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
405  /* @brief Has EEPROM region protection (register FEPROT). */
406  #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
407  /* @brief Has data flash region protection (register FDPROT). */
408  #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
409  /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
410  #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
411  /* @brief Has flash cache control in FMC module. */
412  #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
413  /* @brief Has flash cache control in MCM module. */
414  #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
415  /* @brief P-Flash start address. */
416  #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
417  /* @brief P-Flash block count. */
418  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
419  /* @brief P-Flash block size. */
420  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768)
421  /* @brief P-Flash sector size. */
422  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
423  /* @brief P-Flash write unit size. */
424  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
425  /* @brief P-Flash data path width. */
426  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
427  /* @brief P-Flash block swap feature. */
428  #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
429  /* @brief Has FlexNVM memory. */
430  #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
431  /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
432  #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
433  /* @brief FlexNVM block count. */
434  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
435  /* @brief FlexNVM block size. */
436  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
437  /* @brief FlexNVM sector size. */
438  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
439  /* @brief FlexNVM write unit size. */
440  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
441  /* @brief FlexNVM data path width. */
442  #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
443  /* @brief Has FlexRAM memory. */
444  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
445  /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
446  #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
447  /* @brief FlexRAM size. */
448  #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
449  /* @brief Has 0x00 Read 1s Block command. */
450  #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
451  /* @brief Has 0x01 Read 1s Section command. */
452  #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
453  /* @brief Has 0x02 Program Check command. */
454  #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
455  /* @brief Has 0x03 Read Resource command. */
456  #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
457  /* @brief Has 0x06 Program Longword command. */
458  #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
459  /* @brief Has 0x07 Program Phrase command. */
460  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
461  /* @brief Has 0x08 Erase Flash Block command. */
462  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
463  /* @brief Has 0x09 Erase Flash Sector command. */
464  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
465  /* @brief Has 0x0B Program Section command. */
466  #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
467  /* @brief Has 0x40 Read 1s All Blocks command. */
468  #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
469  /* @brief Has 0x41 Read Once command. */
470  #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
471  /* @brief Has 0x43 Program Once command. */
472  #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
473  /* @brief Has 0x44 Erase All Blocks command. */
474  #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
475  /* @brief Has 0x45 Verify Backdoor Access Key command. */
476  #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
477  /* @brief Has 0x46 Swap Control command. */
478  #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
479  /* @brief Has 0x80 Program Partition command. */
480  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
481  /* @brief Has 0x81 Set FlexRAM Function command. */
482  #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
483  /* @brief P-Flash Erase/Read 1st all block command address alignment. */
484  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
485  /* @brief P-Flash Erase sector command address alignment. */
486  #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
487  /* @brief P-Flash Rrogram/Verify section command address alignment. */
488  #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
489  /* @brief P-Flash Read resource command address alignment. */
490  #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
491  /* @brief P-Flash Program check command address alignment. */
492  #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
493  /* @brief P-Flash Program check command address alignment. */
494  #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
495  /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
496  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
497  /* @brief FlexNVM Erase sector command address alignment. */
498  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
499  /* @brief FlexNVM Rrogram/Verify section command address alignment. */
500  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
501  /* @brief FlexNVM Read resource command address alignment. */
502  #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
503  /* @brief FlexNVM Program check command address alignment. */
504  #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
505  /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
506  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
507  /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
508  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
509  /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
510  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
511  /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
512  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
513  /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
514  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
515  /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
516  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
517  /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
518  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
519  /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
520  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
521  /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
522  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
523  /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
524  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
525  /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
526  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
527  /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
528  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
529  /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
530  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
531  /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
532  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
533  /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
534  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
535  /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
536  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
537  /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
538  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
539  /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
540  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
541  /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
542  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
543  /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
544  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
545  /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
546  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
547  /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
548  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
549  /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
550  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
551  /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
552  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
553  /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
554  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
555  /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
556  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
557  /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
558  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
559  /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
560  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
561  /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
562  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
563  /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
564  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
565  /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
566  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
567  /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
568  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
569 #elif defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z64VLK4)
570  /* @brief Is of type FTFA. */
571  #define FSL_FEATURE_FLASH_IS_FTFA (1)
572  /* @brief Is of type FTFE. */
573  #define FSL_FEATURE_FLASH_IS_FTFE (0)
574  /* @brief Is of type FTFL. */
575  #define FSL_FEATURE_FLASH_IS_FTFL (0)
576  /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
577  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
578  /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
579  #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
580  /* @brief Has EEPROM region protection (register FEPROT). */
581  #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
582  /* @brief Has data flash region protection (register FDPROT). */
583  #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
584  /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
585  #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
586  /* @brief Has flash cache control in FMC module. */
587  #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
588  /* @brief Has flash cache control in MCM module. */
589  #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
590  /* @brief P-Flash start address. */
591  #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
592  /* @brief P-Flash block count. */
593  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
594  /* @brief P-Flash block size. */
595  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
596  /* @brief P-Flash sector size. */
597  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
598  /* @brief P-Flash write unit size. */
599  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
600  /* @brief P-Flash data path width. */
601  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
602  /* @brief P-Flash block swap feature. */
603  #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
604  /* @brief Has FlexNVM memory. */
605  #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
606  /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
607  #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
608  /* @brief FlexNVM block count. */
609  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
610  /* @brief FlexNVM block size. */
611  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
612  /* @brief FlexNVM sector size. */
613  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
614  /* @brief FlexNVM write unit size. */
615  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
616  /* @brief FlexNVM data path width. */
617  #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
618  /* @brief Has FlexRAM memory. */
619  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
620  /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
621  #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
622  /* @brief FlexRAM size. */
623  #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
624  /* @brief Has 0x00 Read 1s Block command. */
625  #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
626  /* @brief Has 0x01 Read 1s Section command. */
627  #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
628  /* @brief Has 0x02 Program Check command. */
629  #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
630  /* @brief Has 0x03 Read Resource command. */
631  #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
632  /* @brief Has 0x06 Program Longword command. */
633  #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
634  /* @brief Has 0x07 Program Phrase command. */
635  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
636  /* @brief Has 0x08 Erase Flash Block command. */
637  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
638  /* @brief Has 0x09 Erase Flash Sector command. */
639  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
640  /* @brief Has 0x0B Program Section command. */
641  #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
642  /* @brief Has 0x40 Read 1s All Blocks command. */
643  #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
644  /* @brief Has 0x41 Read Once command. */
645  #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
646  /* @brief Has 0x43 Program Once command. */
647  #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
648  /* @brief Has 0x44 Erase All Blocks command. */
649  #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
650  /* @brief Has 0x45 Verify Backdoor Access Key command. */
651  #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
652  /* @brief Has 0x46 Swap Control command. */
653  #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
654  /* @brief Has 0x80 Program Partition command. */
655  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
656  /* @brief Has 0x81 Set FlexRAM Function command. */
657  #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
658  /* @brief P-Flash Erase/Read 1st all block command address alignment. */
659  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
660  /* @brief P-Flash Erase sector command address alignment. */
661  #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
662  /* @brief P-Flash Rrogram/Verify section command address alignment. */
663  #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
664  /* @brief P-Flash Read resource command address alignment. */
665  #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
666  /* @brief P-Flash Program check command address alignment. */
667  #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
668  /* @brief P-Flash Program check command address alignment. */
669  #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
670  /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
671  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
672  /* @brief FlexNVM Erase sector command address alignment. */
673  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
674  /* @brief FlexNVM Rrogram/Verify section command address alignment. */
675  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
676  /* @brief FlexNVM Read resource command address alignment. */
677  #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
678  /* @brief FlexNVM Program check command address alignment. */
679  #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
680  /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
681  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
682  /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
683  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
684  /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
685  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
686  /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
687  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
688  /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
689  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
690  /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
691  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
692  /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
693  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
694  /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
695  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
696  /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
697  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
698  /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
699  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
700  /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
701  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
702  /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
703  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
704  /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
705  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
706  /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
707  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
708  /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
709  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
710  /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
711  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
712  /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
713  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
714  /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
715  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
716  /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
717  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
718  /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
719  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
720  /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
721  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
722  /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
723  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
724  /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
725  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
726  /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
727  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
728  /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
729  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
730  /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
731  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
732  /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
733  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
734  /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
735  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
736  /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
737  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
738  /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
739  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
740  /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
741  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
742  /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
743  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
744 #elif defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z128VLK4)
745  /* @brief Is of type FTFA. */
746  #define FSL_FEATURE_FLASH_IS_FTFA (1)
747  /* @brief Is of type FTFE. */
748  #define FSL_FEATURE_FLASH_IS_FTFE (0)
749  /* @brief Is of type FTFL. */
750  #define FSL_FEATURE_FLASH_IS_FTFL (0)
751  /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
752  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
753  /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
754  #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
755  /* @brief Has EEPROM region protection (register FEPROT). */
756  #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
757  /* @brief Has data flash region protection (register FDPROT). */
758  #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
759  /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
760  #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
761  /* @brief Has flash cache control in FMC module. */
762  #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
763  /* @brief Has flash cache control in MCM module. */
764  #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
765  /* @brief P-Flash start address. */
766  #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
767  /* @brief P-Flash block count. */
768  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
769  /* @brief P-Flash block size. */
770  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
771  /* @brief P-Flash sector size. */
772  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
773  /* @brief P-Flash write unit size. */
774  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
775  /* @brief P-Flash data path width. */
776  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
777  /* @brief P-Flash block swap feature. */
778  #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
779  /* @brief Has FlexNVM memory. */
780  #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
781  /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
782  #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
783  /* @brief FlexNVM block count. */
784  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
785  /* @brief FlexNVM block size. */
786  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
787  /* @brief FlexNVM sector size. */
788  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
789  /* @brief FlexNVM write unit size. */
790  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
791  /* @brief FlexNVM data path width. */
792  #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
793  /* @brief Has FlexRAM memory. */
794  #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
795  /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
796  #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
797  /* @brief FlexRAM size. */
798  #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
799  /* @brief Has 0x00 Read 1s Block command. */
800  #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
801  /* @brief Has 0x01 Read 1s Section command. */
802  #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
803  /* @brief Has 0x02 Program Check command. */
804  #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
805  /* @brief Has 0x03 Read Resource command. */
806  #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
807  /* @brief Has 0x06 Program Longword command. */
808  #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
809  /* @brief Has 0x07 Program Phrase command. */
810  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
811  /* @brief Has 0x08 Erase Flash Block command. */
812  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
813  /* @brief Has 0x09 Erase Flash Sector command. */
814  #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
815  /* @brief Has 0x0B Program Section command. */
816  #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
817  /* @brief Has 0x40 Read 1s All Blocks command. */
818  #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
819  /* @brief Has 0x41 Read Once command. */
820  #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
821  /* @brief Has 0x43 Program Once command. */
822  #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
823  /* @brief Has 0x44 Erase All Blocks command. */
824  #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
825  /* @brief Has 0x45 Verify Backdoor Access Key command. */
826  #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
827  /* @brief Has 0x46 Swap Control command. */
828  #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
829  /* @brief Has 0x80 Program Partition command. */
830  #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
831  /* @brief Has 0x81 Set FlexRAM Function command. */
832  #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
833  /* @brief P-Flash Erase/Read 1st all block command address alignment. */
834  #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
835  /* @brief P-Flash Erase sector command address alignment. */
836  #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
837  /* @brief P-Flash Rrogram/Verify section command address alignment. */
838  #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
839  /* @brief P-Flash Read resource command address alignment. */
840  #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
841  /* @brief P-Flash Program check command address alignment. */
842  #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
843  /* @brief P-Flash Program check command address alignment. */
844  #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
845  /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
846  #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
847  /* @brief FlexNVM Erase sector command address alignment. */
848  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
849  /* @brief FlexNVM Rrogram/Verify section command address alignment. */
850  #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
851  /* @brief FlexNVM Read resource command address alignment. */
852  #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
853  /* @brief FlexNVM Program check command address alignment. */
854  #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
855  /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
856  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
857  /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
858  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
859  /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
860  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
861  /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
862  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
863  /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
864  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
865  /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
866  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
867  /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
868  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
869  /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
870  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
871  /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
872  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
873  /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
874  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
875  /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
876  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
877  /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
878  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
879  /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
880  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
881  /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
882  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
883  /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
884  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
885  /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
886  #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
887  /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
888  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
889  /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
890  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
891  /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
892  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
893  /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
894  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
895  /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
896  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
897  /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
898  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
899  /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
900  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
901  /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
902  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
903  /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
904  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
905  /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
906  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
907  /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
908  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
909  /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
910  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
911  /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
912  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
913  /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
914  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
915  /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
916  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
917  /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
918  #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
919 #endif
920 
921 /* GPIO module features */
922 
923 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
924 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
925 /* @brief Has port input disable register (PIDR). */
926 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
927 /* @brief Has dedicated interrupt vector. */
928 #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
929 
930 /* I2C module features */
931 
932 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
933 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
934 /* @brief Maximum supported baud rate in kilobit per second. */
935 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
936 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
937 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
938 /* @brief Has DMA support (register bit C1[DMAEN]). */
939 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
940 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
941 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0)
942 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
943 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
944 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
945 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
946 /* @brief Maximum width of the glitch filter in number of bus clocks. */
947 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
948 /* @brief Has control of the drive capability of the I2C pins. */
949 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
950 /* @brief Has double buffering support (register S2). */
951 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
952 
953 /* LLWU module features */
954 
955 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
956 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
957 /* @brief Has pins 8-15 connected to LLWU device. */
958 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
959 /* @brief Maximum number of internal modules connected to LLWU device. */
960 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
961 /* @brief Number of digital filters. */
962 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
963 /* @brief Has MF5 register. */
964 #define FSL_FEATURE_LLWU_HAS_MF (0)
965 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
966 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
967 /* @brief Has external pin 0 connected to LLWU device. */
968 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
969 /* @brief Index of port of external pin. */
970 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
971 /* @brief Number of external pin port on specified port. */
972 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
973 /* @brief Has external pin 1 connected to LLWU device. */
974 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
975 /* @brief Index of port of external pin. */
976 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
977 /* @brief Number of external pin port on specified port. */
978 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
979 /* @brief Has external pin 2 connected to LLWU device. */
980 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
981 /* @brief Index of port of external pin. */
982 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
983 /* @brief Number of external pin port on specified port. */
984 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
985 /* @brief Has external pin 3 connected to LLWU device. */
986 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
987 /* @brief Index of port of external pin. */
988 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
989 /* @brief Number of external pin port on specified port. */
990 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
991 /* @brief Has external pin 4 connected to LLWU device. */
992 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
993 /* @brief Index of port of external pin. */
994 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
995 /* @brief Number of external pin port on specified port. */
996 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
997 /* @brief Has external pin 5 connected to LLWU device. */
998 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
999 /* @brief Index of port of external pin. */
1000 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
1001 /* @brief Number of external pin port on specified port. */
1002 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
1003 /* @brief Has external pin 6 connected to LLWU device. */
1004 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
1005 /* @brief Index of port of external pin. */
1006 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
1007 /* @brief Number of external pin port on specified port. */
1008 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
1009 /* @brief Has external pin 7 connected to LLWU device. */
1010 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
1011 /* @brief Index of port of external pin. */
1012 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
1013 /* @brief Number of external pin port on specified port. */
1014 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
1015 /* @brief Has external pin 8 connected to LLWU device. */
1016 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
1017 /* @brief Index of port of external pin. */
1018 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
1019 /* @brief Number of external pin port on specified port. */
1020 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
1021 /* @brief Has external pin 9 connected to LLWU device. */
1022 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
1023 /* @brief Index of port of external pin. */
1024 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
1025 /* @brief Number of external pin port on specified port. */
1026 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
1027 /* @brief Has external pin 10 connected to LLWU device. */
1028 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
1029 /* @brief Index of port of external pin. */
1030 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
1031 /* @brief Number of external pin port on specified port. */
1032 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
1033 /* @brief Has external pin 11 connected to LLWU device. */
1034 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
1035 /* @brief Index of port of external pin. */
1036 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
1037 /* @brief Number of external pin port on specified port. */
1038 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
1039 /* @brief Has external pin 12 connected to LLWU device. */
1040 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
1041 /* @brief Index of port of external pin. */
1042 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
1043 /* @brief Number of external pin port on specified port. */
1044 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
1045 /* @brief Has external pin 13 connected to LLWU device. */
1046 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
1047 /* @brief Index of port of external pin. */
1048 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
1049 /* @brief Number of external pin port on specified port. */
1050 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
1051 /* @brief Has external pin 14 connected to LLWU device. */
1052 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1053 /* @brief Index of port of external pin. */
1054 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1055 /* @brief Number of external pin port on specified port. */
1056 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1057 /* @brief Has external pin 15 connected to LLWU device. */
1058 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1059 /* @brief Index of port of external pin. */
1060 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1061 /* @brief Number of external pin port on specified port. */
1062 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1063 /* @brief Has external pin 16 connected to LLWU device. */
1064 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
1065 /* @brief Index of port of external pin. */
1066 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
1067 /* @brief Number of external pin port on specified port. */
1068 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
1069 /* @brief Has external pin 17 connected to LLWU device. */
1070 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
1071 /* @brief Index of port of external pin. */
1072 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
1073 /* @brief Number of external pin port on specified port. */
1074 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
1075 /* @brief Has external pin 18 connected to LLWU device. */
1076 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
1077 /* @brief Index of port of external pin. */
1078 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
1079 /* @brief Number of external pin port on specified port. */
1080 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
1081 /* @brief Has external pin 19 connected to LLWU device. */
1082 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
1083 /* @brief Index of port of external pin. */
1084 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
1085 /* @brief Number of external pin port on specified port. */
1086 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
1087 /* @brief Has external pin 20 connected to LLWU device. */
1088 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
1089 /* @brief Index of port of external pin. */
1090 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
1091 /* @brief Number of external pin port on specified port. */
1092 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
1093 /* @brief Has external pin 21 connected to LLWU device. */
1094 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
1095 /* @brief Index of port of external pin. */
1096 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
1097 /* @brief Number of external pin port on specified port. */
1098 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
1099 /* @brief Has external pin 22 connected to LLWU device. */
1100 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
1101 /* @brief Index of port of external pin. */
1102 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
1103 /* @brief Number of external pin port on specified port. */
1104 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
1105 /* @brief Has external pin 23 connected to LLWU device. */
1106 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
1107 /* @brief Index of port of external pin. */
1108 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
1109 /* @brief Number of external pin port on specified port. */
1110 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
1111 /* @brief Has external pin 24 connected to LLWU device. */
1112 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
1113 /* @brief Index of port of external pin. */
1114 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
1115 /* @brief Number of external pin port on specified port. */
1116 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
1117 /* @brief Has external pin 25 connected to LLWU device. */
1118 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
1119 /* @brief Index of port of external pin. */
1120 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1121 /* @brief Number of external pin port on specified port. */
1122 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1123 /* @brief Has external pin 26 connected to LLWU device. */
1124 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1125 /* @brief Index of port of external pin. */
1126 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1127 /* @brief Number of external pin port on specified port. */
1128 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1129 /* @brief Has external pin 27 connected to LLWU device. */
1130 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1131 /* @brief Index of port of external pin. */
1132 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1133 /* @brief Number of external pin port on specified port. */
1134 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1135 /* @brief Has external pin 28 connected to LLWU device. */
1136 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1137 /* @brief Index of port of external pin. */
1138 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1139 /* @brief Number of external pin port on specified port. */
1140 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1141 /* @brief Has external pin 29 connected to LLWU device. */
1142 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1143 /* @brief Index of port of external pin. */
1144 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1145 /* @brief Number of external pin port on specified port. */
1146 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1147 /* @brief Has external pin 30 connected to LLWU device. */
1148 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1149 /* @brief Index of port of external pin. */
1150 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1151 /* @brief Number of external pin port on specified port. */
1152 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1153 /* @brief Has external pin 31 connected to LLWU device. */
1154 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1155 /* @brief Index of port of external pin. */
1156 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1157 /* @brief Number of external pin port on specified port. */
1158 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1159 /* @brief Has internal module 0 connected to LLWU device. */
1160 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1161 /* @brief Has internal module 1 connected to LLWU device. */
1162 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1163 /* @brief Has internal module 2 connected to LLWU device. */
1164 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
1165 /* @brief Has internal module 3 connected to LLWU device. */
1166 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
1167 /* @brief Has internal module 4 connected to LLWU device. */
1168 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
1169 /* @brief Has internal module 5 connected to LLWU device. */
1170 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
1171 /* @brief Has internal module 6 connected to LLWU device. */
1172 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1173 /* @brief Has internal module 7 connected to LLWU device. */
1174 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
1175 
1176 /* LPTMR module features */
1177 
1178 /* @brief Has shared interrupt handler with another LPTMR module. */
1179 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1180 
1181 /* MCG module features */
1182 
1183 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1184 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
1185 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1186 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
1187 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1188 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
1189 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1190 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
1191 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1192 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
1193 /* @brief The PLL clock is divided by 2 before VCO divider. */
1194 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
1195 /* @brief FRDIV supports 1280. */
1196 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1197 /* @brief FRDIV supports 1536. */
1198 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1199 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1200 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
1201 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1202 #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
1203 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1204 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
1205 /* @brief Has 48MHz internal oscillator. */
1206 #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
1207 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1208 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
1209 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1210 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
1211 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1212 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
1213 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1214 #define FSL_FEATURE_MCG_USE_OSCSEL (0)
1215 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1216 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1217 /* @brief TBD */
1218 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1219 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
1220 #define FSL_FEATURE_MCG_HAS_PLL (1)
1221 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1222 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
1223 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1224 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
1225 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1226 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
1227 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1228 #define FSL_FEATURE_MCG_HAS_FLL (1)
1229 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1230 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1231 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1232 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1233 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1234 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
1235 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1236 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1237 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1238 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1239 /* @brief Has external clock monitor (register bit C6[CME]). */
1240 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1241 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1242 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1243 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1244 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1245 /* @brief Has PEI mode or PBI mode. */
1246 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1247 /* @brief Reset clock mode is BLPI. */
1248 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1249 
1250 /* interrupt module features */
1251 
1252 /* @brief Lowest interrupt request number. */
1253 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1254 /* @brief Highest interrupt request number. */
1255 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
1256 
1257 /* OSC module features */
1258 
1259 /* @brief Has OSC1 external oscillator. */
1260 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
1261 /* @brief Has OSC0 external oscillator. */
1262 #define FSL_FEATURE_OSC_HAS_OSC0 (1)
1263 /* @brief Has OSC external oscillator (without index). */
1264 #define FSL_FEATURE_OSC_HAS_OSC (0)
1265 /* @brief Number of OSC external oscillators. */
1266 #define FSL_FEATURE_OSC_OSC_COUNT (1)
1267 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1268 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
1269 
1270 /* PIT module features */
1271 
1272 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1273 #define FSL_FEATURE_PIT_TIMER_COUNT (2)
1274 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1275 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
1276 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1277 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1278 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1279 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
1280 
1281 /* PMC module features */
1282 
1283 /* @brief Has Bandgap Enable In VLPx Operation support. */
1284 #define FSL_FEATURE_PMC_HAS_BGEN (1)
1285 /* @brief Has Bandgap Buffer Drive Select. */
1286 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
1287 
1288 /* PORT module features */
1289 
1290 /* @brief Has control lock (register bit PCR[LK]). */
1291 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
1292 /* @brief Has open drain control (register bit PCR[ODE]). */
1293 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
1294 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1295 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
1296 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
1297 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1298 /* @brief Has pull resistor selection available. */
1299 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
1300 /* @brief Has pull resistor enable (register bit PCR[PE]). */
1301 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1302 /* @brief Has slew rate control (register bit PCR[SRE]). */
1303 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1304 /* @brief Has passive filter (register bit field PCR[PFE]). */
1305 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1306 /* @brief Has drive strength control (register bit PCR[DSE]). */
1307 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1308 /* @brief Has separate drive strength register (HDRVE). */
1309 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1310 /* @brief Has glitch filter (register IOFLT). */
1311 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1312 /* @brief Defines width of PCR[MUX] field. */
1313 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1314 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1315 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1316 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1317 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1318 
1319 /* RCM module features */
1320 
1321 /* @brief Has Loss-of-Lock Reset support. */
1322 #define FSL_FEATURE_RCM_HAS_LOL (1)
1323 /* @brief Has Loss-of-Clock Reset support. */
1324 #define FSL_FEATURE_RCM_HAS_LOC (1)
1325 /* @brief Has JTAG generated Reset support. */
1326 #define FSL_FEATURE_RCM_HAS_JTAG (0)
1327 /* @brief Has EzPort generated Reset support. */
1328 #define FSL_FEATURE_RCM_HAS_EZPORT (0)
1329 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1330 #define FSL_FEATURE_RCM_HAS_EZPMS (0)
1331 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1332 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1333 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1334 #define FSL_FEATURE_RCM_HAS_SSRS (0)
1335 
1336 /* RTC module features */
1337 
1338 /* @brief Has wakeup pin (bit field CR[WPS]). */
1339 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1340 /* @brief Has low power features (registers MER, MCLR and MCHR). */
1341 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1342 /* @brief Has read/write access control (registers WAR and RAR). */
1343 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
1344 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1345 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
1346 
1347 /* SIM module features */
1348 
1349 /* @brief Has USB FS divider. */
1350 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1351 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1352 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
1353 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1354 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1355 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1356 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1357 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1358 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1359 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1360 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1361 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1362 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1363 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1364 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1365 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1366 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1367 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1368 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1369 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1370 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1371 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1372 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1373 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1374 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1375 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1376 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
1377 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1378 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1379 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1380 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
1381 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1382 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1)
1383 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1384 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1)
1385 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1386 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
1387 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1388 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1389 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1390 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1391 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1392 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1393 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1394 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1395 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1396 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1397 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1398 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1399 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1400 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1401 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1402 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1403 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1404 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1405 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1406 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1407 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1408 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
1409 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1410 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1411 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1412 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1413 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1414 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1)
1415 /* @brief Has FTM module(s) configuration. */
1416 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1417 /* @brief Number of FTM modules. */
1418 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1419 /* @brief Number of FTM triggers with selectable source. */
1420 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1421 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1422 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1423 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1424 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1425 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1426 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1427 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1428 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1429 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1430 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1431 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1432 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1433 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1434 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1435 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1436 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1437 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1438 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1439 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1440 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1441 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1442 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1443 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1444 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1445 /* @brief Has TPM module(s) configuration. */
1446 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1447 /* @brief The highest TPM module index. */
1448 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1449 /* @brief Has TPM module with index 0. */
1450 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
1451 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1452 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
1453 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1454 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
1455 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1456 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1457 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1458 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
1459 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1460 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
1461 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1462 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
1463 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1464 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
1465 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1466 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1467 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1468 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1469 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1470 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1471 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1472 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1473 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1474 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1475 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1476 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1477 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1478 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1479 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1480 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1481 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1482 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1483 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1484 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1485 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1486 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1487 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1488 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1489 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1490 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1491 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1492 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1493 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1494 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1495 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1496 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
1497 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1498 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1499 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1500 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1501 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1502 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
1503 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1504 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1505 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1506 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1507 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1508 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1509 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1510 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
1511 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1512 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1513 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1514 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1515 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1516 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1517 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1518 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1519 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1520 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1521 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1522 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1523 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1524 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1525 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1526 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1527 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1528 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1529 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1530 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1531 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1532 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1533 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1534 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1535 /* @brief Has device die ID (register bit field SDID[DIEID]). */
1536 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1537 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1538 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
1539 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1540 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1541 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1542 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1543 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1544 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1545 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1546 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1547 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1548 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1549 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1550 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1551 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1552 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1553 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1554 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1555 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1556 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1557 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1558 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1559 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1560 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1561 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1562 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1563 /* @brief Has miscellanious control register (register MCR). */
1564 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1565 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1566 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
1567 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1568 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1569 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1570 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1571 
1572 /* SMC module features */
1573 
1574 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1575 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1576 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1577 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
1578 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1579 #define FSL_FEATURE_SMC_HAS_PORPO (1)
1580 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1581 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
1582 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1583 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1584 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1585 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1586 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1587 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
1588 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1589 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1590 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1591 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
1592 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1593 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1594 /* @brief Has stop submode 0(VLLS0). */
1595 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1596 /* @brief Has stop submode 2(VLLS2). */
1597 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
1598 
1599 /* SPI module features */
1600 
1601 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
1602 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
1603 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
1604 #define FSL_FEATURE_SPI_FIFO_SIZE (0)
1605 #define FSL_FEATURE_SPI_FIFO_SIZEx { 0, 0 }
1606 /* @brief Maximum transfer data width in bits. */
1607 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
1608 /* @brief The data register name has postfix (L as low and H as high). */
1609 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
1610 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1611 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1612 /* @brief Has 16-bit data transfer support. */
1613 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
1614 
1615 /* SysTick module features */
1616 
1617 /* @brief Systick has external reference clock. */
1618 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1619 /* @brief Systick external reference clock is core clock divided by this value. */
1620 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1621 
1622 /* TPM module features */
1623 
1624 /* @brief Bus clock is the source clock for the module. */
1625 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
1626 /* @brief Number of channels. */
1627 #define FSL_FEATURE_TPM_CHANNEL_COUNT (6)
1628 #define FSL_FEATURE_TPM_CHANNEL_COUNTx { 6, 2, 2 }
1629 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1630 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1631 
1632 /* TSI module features */
1633 
1634 /* @brief TSI module version. */
1635 #define FSL_FEATURE_TSI_VERSION (4)
1636 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
1637 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
1638 /* @brief Number of TSI channels. */
1639 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
1640 
1641 /* LPSCI module features */
1642 
1643 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1644 #define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1645 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1646 #define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1)
1647 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1648 #define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
1649 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1650 #define FSL_FEATURE_LPSCI_HAS_FIFO (0)
1651 /* @brief Hardware flow control (RTS, CTS) is supported. */
1652 #define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0)
1653 /* @brief Infrared (modulation) is supported. */
1654 #define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0)
1655 /* @brief 2 bits long stop bit is available. */
1656 #define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1657 /* @brief Maximal data width without parity bit. */
1658 #define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1)
1659 /* @brief Baud rate fine adjustment is available. */
1660 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
1661 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1662 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
1663 /* @brief Baud rate oversampling is available. */
1664 #define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1)
1665 /* @brief Baud rate oversampling is available. */
1666 #define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
1667 /* @brief Peripheral type. */
1668 #define FSL_FEATURE_LPSCI_IS_SCI (1)
1669 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1670 #define FSL_FEATURE_LPSCI_FIFO_SIZE (0)
1671 /* @brief Maximal data width without parity bit. */
1672 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
1673 /* @brief Maximal data width with parity bit. */
1674 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9)
1675 /* @brief Supports two match addresses to filter incoming frames. */
1676 #define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1)
1677 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1678 #define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1)
1679 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1680 #define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0)
1681 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1682 #define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1)
1683 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1684 #define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0)
1685 /* @brief Has improved smart card (ISO7816 protocol) support. */
1686 #define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1687 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1688 #define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1689 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1690 #define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0)
1691 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1692 #define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1)
1693 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1694 #define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0)
1695 /* @brief Has separate DMA RX and TX requests. */
1696 #define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1697  ((x) == 0 ? (1) : (-1))
1698 
1699 /* UART module features */
1700 
1701 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1702 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1703 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1704 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1705 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1706 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
1707 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1708 #define FSL_FEATURE_UART_HAS_FIFO (0)
1709 /* @brief Hardware flow control (RTS, CTS) is supported. */
1710 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
1711 /* @brief Infrared (modulation) is supported. */
1712 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
1713 /* @brief 2 bits long stop bit is available. */
1714 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1715 /* @brief Maximal data width without parity bit. */
1716 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
1717 /* @brief Baud rate fine adjustment is available. */
1718 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
1719 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1720 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1721 /* @brief Baud rate oversampling is available. */
1722 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1)
1723 /* @brief Baud rate oversampling is available. */
1724 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
1725 /* @brief Peripheral type. */
1726 #define FSL_FEATURE_UART_IS_SCI (1)
1727 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1728 #define FSL_FEATURE_UART_FIFO_SIZE (0)
1729 /* @brief Maximal data width without parity bit. */
1730 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
1731 /* @brief Maximal data width with parity bit. */
1732 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8)
1733 /* @brief Supports two match addresses to filter incoming frames. */
1734 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0)
1735 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1736 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1737 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1738 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1739 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1740 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0)
1741 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1742 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
1743 /* @brief Has improved smart card (ISO7816 protocol) support. */
1744 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1745 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1746 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1747 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1748 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1749 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1750 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1751 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1752 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1753 /* @brief Has separate DMA RX and TX requests. */
1754 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1755  ((x) == 1 ? (1) : \
1756  ((x) == 2 ? (1) : (-1)))
1757 
1758 /* USB module features */
1759 
1760 /* @brief HOST mode enabled */
1761 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
1762 /* @brief OTG mode enabled */
1763 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
1764 /* @brief Size of the USB dedicated RAM */
1765 #define FSL_FEATURE_USB_KHCI_USB_RAM (0)
1766 /* @brief Has KEEP_ALIVE_CTRL register */
1767 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
1768 /* @brief Has the Dynamic SOF threshold compare support */
1769 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
1770 /* @brief Has the VBUS detect support */
1771 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
1772 /* @brief Has the IRC48M module clock support */
1773 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0)
1774 
1775 #endif /* __FSL_MKL25Z4_FEATURES_H__ */
1776 
1777 /*******************************************************************************
1778  * EOF
1779  ******************************************************************************/
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