Contiki 3.x
system_MKL25Z4.h
1 /*
2 ** ###################################################################
3 ** Processors: MKL25Z128FM4
4 ** MKL25Z128FT4
5 ** MKL25Z128LH4
6 ** MKL25Z128VLK4
7 **
8 ** Compilers: Keil ARM C/C++ Compiler
9 ** Freescale C/C++ for Embedded ARM
10 ** GNU C Compiler
11 ** GNU C Compiler - CodeSourcery Sourcery G++
12 ** IAR ANSI C/C++ Compiler for ARM
13 **
14 ** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
15 ** Version: rev. 2.5, 2015-02-19
16 ** Build: b150224
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
24 ** All rights reserved.
25 **
26 ** Redistribution and use in source and binary forms, with or without modification,
27 ** are permitted provided that the following conditions are met:
28 **
29 ** o Redistributions of source code must retain the above copyright notice, this list
30 ** of conditions and the following disclaimer.
31 **
32 ** o Redistributions in binary form must reproduce the above copyright notice, this
33 ** list of conditions and the following disclaimer in the documentation and/or
34 ** other materials provided with the distribution.
35 **
36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
37 ** contributors may be used to endorse or promote products derived from this
38 ** software without specific prior written permission.
39 **
40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 **
51 ** http: www.freescale.com
52 ** mail: support@freescale.com
53 **
54 ** Revisions:
55 ** - rev. 1.0 (2012-06-13)
56 ** Initial version.
57 ** - rev. 1.1 (2012-06-21)
58 ** Update according to reference manual rev. 1.
59 ** - rev. 1.2 (2012-08-01)
60 ** Device type UARTLP changed to UART0.
61 ** - rev. 1.3 (2012-10-04)
62 ** Update according to reference manual rev. 3.
63 ** - rev. 1.4 (2012-11-22)
64 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
65 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
66 ** - rev. 1.5 (2013-04-05)
67 ** Changed start of doxygen comment.
68 ** - rev. 2.0 (2013-10-29)
69 ** Register accessor macros added to the memory map.
70 ** Symbols for Processor Expert memory map compatibility added to the memory map.
71 ** Startup file for gcc has been updated according to CMSIS 3.2.
72 ** System initialization updated.
73 ** - rev. 2.1 (2014-07-16)
74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
75 ** System initialization and startup updated.
76 ** - rev. 2.2 (2014-08-22)
77 ** System initialization updated - default clock config changed.
78 ** - rev. 2.3 (2014-08-28)
79 ** Update of startup files - possibility to override DefaultISR added.
80 ** - rev. 2.4 (2014-10-14)
81 ** Interrupt INT_LPTimer renamed to INT_LPTMR0.
82 ** - rev. 2.5 (2015-02-19)
83 ** Renamed interrupt vector LLW to LLWU.
84 **
85 ** ###################################################################
86 */
87 
88 /*!
89  * @file MKL25Z4
90  * @version 2.5
91  * @date 2015-02-19
92  * @brief Device specific configuration file for MKL25Z4 (header file)
93  *
94  * Provides a system configuration function and a global variable that contains
95  * the system frequency. It configures the device and initializes the oscillator
96  * (PLL) that is part of the microcontroller device.
97  */
98 
99 #ifndef SYSTEM_MKL25Z4_H_
100 #define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
101 
102 #include "contiki-conf.h"
103 
104 #include <stdint.h>
105 
106 
107 #ifdef __cplusplus
108 extern "C" {
109 #endif
110 
111 
112 
113 
114 #ifndef DISABLE_WDOG
115  #define DISABLE_WDOG 1
116 #endif
117 
118 
119 
120 
121 /* MCG mode constants */
122 
123 #define MCG_MODE_FEI 0U
124 #define MCG_MODE_FBI 1U
125 #define MCG_MODE_BLPI 2U
126 #define MCG_MODE_FEE 3U
127 #define MCG_MODE_FBE 4U
128 #define MCG_MODE_BLPE 5U
129 #define MCG_MODE_PBE 6U
130 #define MCG_MODE_PEE 7U
131 
132 /* Predefined clock setups
133  0 ... Default part configuration
134  Multipurpose Clock Generator (MCG) in FEI mode.
135  Reference clock source for MCG module: Slow internal reference clock
136  Core clock = 20.97152MHz
137  Bus clock = 20.97152MHz
138  1 ... Maximum achievable clock frequency configuration
139  Multipurpose Clock Generator (MCG) in PEE mode.
140  Reference clock source for MCG module: System oscillator reference clock
141  Core clock = 48MHz
142  Bus clock = 24MHz
143  2 ... Chip internaly clocked, ready for Very Low Power Run mode
144  Multipurpose Clock Generator (MCG) in BLPI mode.
145  Reference clock source for MCG module: Fast internal reference clock
146  Core clock = 4MHz
147  Bus clock = 0.8MHz
148  3 ... Chip externally clocked, ready for Very Low Power Run mode
149  Multipurpose Clock Generator (MCG) in BLPE mode.
150  Reference clock source for MCG module: System oscillator reference clock
151  Core clock = 4MHz
152  Bus clock = 1MHz
153  4 ... USB clock setup
154  Multipurpose Clock Generator (MCG) in PEE mode.
155  Reference clock source for MCG module: System oscillator reference clock
156  Core clock = 48MHz
157  Bus clock = 24MHz
158  */
159 
160 /* Define clock source values */
161 
162 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
163 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
164 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
165 
166 /* RTC oscillator setting */
167 
168 /* Low power mode enable */
169 #ifndef SYSTEM_SMC_PMPROT_VALUE
170 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
171 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
172 #endif
173 
174 /* Internal reference clock trim */
175 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
176 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
177 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
178 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
179 
180 #ifdef CLOCK_SETUP
181 #if (CLOCK_SETUP == 0)
182  #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
183  #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
184  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=1 */
185  #define SYSTEM_MCG_C1_VALUE 0x07U /* MCG_C1 */
186  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
187  #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
188  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
189  #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
190  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
191  #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
192 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
193  #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
194 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
195  #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
196 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
197  #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
198 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
199  #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
200 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
201  #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
202 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
203  #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
204 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
205  #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
206 #elif (CLOCK_SETUP == 1)
207  #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
208  #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
209  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=1 */
210  #define SYSTEM_MCG_C1_VALUE 0x1BU /* MCG_C1 */
211  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
212  #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
213  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
214  #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
215  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
216  #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
217 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
218  #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
219 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
220  #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
221 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
222  #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
223 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
224  #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
225 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
226  #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
227 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
228  #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
229 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
230  #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
231 #elif (CLOCK_SETUP == 2)
232  #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
233  #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
234  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
235  #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
236  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
237  #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
238  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
239  #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
240  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
241  #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
242 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
243  #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
244 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
245  #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
246 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
247  #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
248 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
249  #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
250 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */
251  #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
252 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
253  #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
254 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
255  #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
256 #elif (CLOCK_SETUP == 3)
257  #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
258  #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
259  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
260  #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
261  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
262  #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
263  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
264  #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
265  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
266  #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
267 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
268  #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
269 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
270  #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
271 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
272  #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
273 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
274  #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
275 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */
276  #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */
277 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
278  #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
279 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
280  #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
281 #elif (CLOCK_SETUP == 4)
282  #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
283  #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
284  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=1 */
285  #define SYSTEM_MCG_C1_VALUE 0x1BU /* MCG_C1 */
286  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
287  #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
288  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
289  #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
290  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
291  #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
292 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
293  #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
294 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
295  #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
296 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
297  #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
298 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
299  #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
300 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
301  #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
302 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
303  #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
304 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
305  #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
306 
307 #endif
308 #else
309  #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
310 #endif
311 
312 /**
313  * @brief System clock frequency (core clock)
314  *
315  * The system clock frequency supplied to the SysTick timer and the processor
316  * core clock. This variable can be used by the user application to setup the
317  * SysTick timer or configure other parameters. It may also be used by debugger to
318  * query the frequency of the debug timer or configure the trace clock speed
319  * SystemCoreClock is initialized with a correct predefined value.
320  */
321 extern uint32_t SystemCoreClock;
322 
323 /**
324  * @brief Setup the microcontroller system.
325  *
326  * Typically this function configures the oscillator (PLL) that is part of the
327  * microcontroller device. For systems with variable clock speed it also updates
328  * the variable SystemCoreClock. SystemInit is called from startup_device file.
329  */
330 void SystemInit (void);
331 
332 /**
333  * @brief Updates the SystemCoreClock variable.
334  *
335  * It must be called whenever the core clock is changed during program
336  * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
337  * the current core clock.
338  */
339 void SystemCoreClockUpdate (void);
340 
341 #ifdef __cplusplus
342 }
343 #endif
344 
345 #endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Update internal SystemCoreClock variable.
Definition: system_ADuCRF101.c:71
SystemInit
void SystemInit(void)
Initialize the system.
Definition: system_ADuCRF101.c:114
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