Contiki 3.x
pka.h
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1 /*
2  * Original file:
3  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4  * All rights reserved.
5  *
6  * Port to Contiki:
7  * Copyright (c) 2014 Andreas Dröscher <contiki@anticat.ch>
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  * notice, this list of conditions and the following disclaimer in the
16  * documentation and/or other materials provided with the distribution.
17  *
18  * 3. Neither the name of the copyright holder nor the names of its
19  * contributors may be used to endorse or promote products derived
20  * from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33  * OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 /**
36  * \addtogroup cc2538
37  * @{
38  *
39  * \defgroup cc2538-pka cc2538 PKA engine
40  *
41  * Driver for the cc2538 PKA engine
42  * @{
43  *
44  * \file
45  * Header file for the cc2538 PKA engine driver
46  */
47 #ifndef PKA_H_
48 #define PKA_H_
49 
50 #include "contiki.h"
51 #include <stdint.h>
52 
53 /*---------------------------------------------------------------------------*/
54 /** \name PKA memory
55  * @{
56  */
57 #define PKA_RAM_BASE 0x44006000 /**< PKA Memory Address */
58 #define PKA_RAM_SIZE 0x800 /**< PKA Memory Size */
59 #define PKA_MAX_CURVE_SIZE 12 /**< Define for the maximum curve
60  size supported by the PKA module
61  in 32 bit word. */
62 #define PKA_MAX_LEN 12 /**< Define for the maximum length of
63  the big number supported by the
64  PKA module in 32 bit word. */
65 /** @} */
66 /*---------------------------------------------------------------------------*/
67 /** \name PKA register offsets
68  * @{
69  */
70 #define PKA_APTR 0x44004000 /**< PKA vector A address During
71  execution of basic PKCP
72  operations, this register is
73  double buffered and can be
74  written with a new value for the
75  next operation; when not
76  written, the value remains
77  intact. During the execution of
78  sequencer-controlled complex
79  operations, this register may
80  not be written and its value is
81  undefined at the conclusion of
82  the operation. The driver
83  software cannot rely on the
84  written value to remain intact. */
85 #define PKA_BPTR 0x44004004 /**< PKA vector B address During
86  execution of basic PKCP
87  operations, this register is
88  double buffered and can be
89  written with a new value for the
90  next operation; when not
91  written, the value remains
92  intact. During the execution of
93  sequencer-controlled complex
94  operations, this register may
95  not be written and its value is
96  undefined at the conclusion of
97  the operation. The driver
98  software cannot rely on the
99  written value to remain intact. */
100 #define PKA_CPTR 0x44004008 /**< PKA vector C address During
101  execution of basic PKCP
102  operations, this register is
103  double buffered and can be
104  written with a new value for the
105  next operation; when not
106  written, the value remains
107  intact. During the execution of
108  sequencer-controlled complex
109  operations, this register may
110  not be written and its value is
111  undefined at the conclusion of
112  the operation. The driver
113  software cannot rely on the
114  written value to remain intact. */
115 #define PKA_DPTR 0x4400400C /**< PKA vector D address During
116  execution of basic PKCP
117  operations, this register is
118  double buffered and can be
119  written with a new value for the
120  next operation; when not
121  written, the value remains
122  intact. During the execution of
123  sequencer-controlled complex
124  operations, this register may
125  not be written and its value is
126  undefined at the conclusion of
127  the operation. The driver
128  software cannot rely on the
129  written value to remain intact. */
130 #define PKA_ALENGTH 0x44004010 /**< PKA vector A length During
131  execution of basic PKCP
132  operations, this register is
133  double buffered and can be
134  written with a new value for the
135  next operation; when not
136  written, the value remains
137  intact. During the execution of
138  sequencer-controlled complex
139  operations, this register may
140  not be written and its value is
141  undefined at the conclusion of
142  the operation. The driver
143  software cannot rely on the
144  written value to remain intact. */
145 #define PKA_BLENGTH 0x44004014 /**< PKA vector B length During
146  execution of basic PKCP
147  operations, this register is
148  double buffered and can be
149  written with a new value for the
150  next operation; when not
151  written, the value remains
152  intact. During the execution of
153  sequencer-controlled complex
154  operations, this register may
155  not be written and its value is
156  undefined at the conclusion of
157  the operation. The driver
158  software cannot rely on the
159  written value to remain intact. */
160 #define PKA_SHIFT 0x44004018 /**< PKA bit shift value For basic
161  PKCP operations, modifying the
162  contents of this register is
163  made impossible while the
164  operation is being performed.
165  For the ExpMod-variable and
166  ExpMod-CRT operations, this
167  register is used to indicate the
168  number of odd powers to use
169  (directly as a value in the
170  range 1-16). For the ModInv and
171  ECC operations, this register is
172  used to hold a completion code. */
173 #define PKA_FUNCTION 0x4400401C /**< PKA function This register
174  contains the control bits to
175  start basic PKCP as well as
176  complex sequencer operations.
177  The run bit can be used to poll
178  for the completion of the
179  operation. Modifying bits [11:0]
180  is made impossible during the
181  execution of a basic PKCP
182  operation. During the execution
183  of sequencer-controlled complex
184  operations, this register is
185  modified; the run and stall
186  result bits are set to zero at
187  the conclusion, but other bits
188  are undefined. Attention:
189  Continuously reading this
190  register to poll the run bit is
191  not allowed when executing
192  complex sequencer operations
193  (the sequencer cannot access the
194  PKCP when this is done). Leave
195  at least one sysclk cycle
196  between poll operations. */
197 #define PKA_COMPARE 0x44004020 /**< PKA compare result This
198  register provides the result of
199  a basic PKCP compare operation.
200  It is updated when the run bit
201  in the PKA_FUNCTION register is
202  reset at the end of that
203  operation. Status after a
204  complex sequencer operation is
205  unknown */
206 #define PKA_MSW 0x44004024 /**< PKA most-significant-word of
207  result vector This register
208  indicates the (word) address in
209  the PKA RAM where the most
210  significant nonzero 32-bit word
211  of the result is stored. Should
212  be ignored for modulo
213  operations. For basic PKCP
214  operations, this register is
215  updated when the run bit in the
216  PKA_FUNCTION register is reset
217  at the end of the operation. For
218  the complex-sequencer controlled
219  operations, updating of the
220  final value matching the actual
221  result is done near the end of
222  the operation; note that the
223  result is only meaningful if no
224  errors were detected and that
225  for ECC operations, the PKA_MSW
226  register will provide
227  information for the x-coordinate
228  of the result point only. */
229 #define PKA_DIVMSW 0x44004028 /**< PKA most-significant-word of
230  divide remainder This register
231  indicates the (32-bit word)
232  address in the PKA RAM where the
233  most significant nonzero 32-bit
234  word of the remainder result for
235  the basic divide and modulo
236  operations is stored. Bits [4:0]
237  are loaded with the bit number
238  of the most-significant nonzero
239  bit in the most-significant
240  nonzero word when MS one control
241  bit is set. For divide, modulo,
242  and MS one reporting, this
243  register is updated when the RUN
244  bit in the PKA_FUNCTION register
245  is reset at the end of the
246  operation. For the complex
247  sequencer controlled operations,
248  updating of bits [4:0] of this
249  register with the
250  most-significant bit location of
251  the actual result is done near
252  the end of the operation. The
253  result is meaningful only if no
254  errors were detected and that
255  for ECC operations; the
256  PKA_DIVMSW register provides
257  information for the x-coordinate
258  of the result point only. */
259 #define PKA_SEQ_CTRL 0x440040C8 /**< PKA sequencer control and
260  status register The sequencer is
261  interfaced with the outside
262  world through a single control
263  and status register. With the
264  exception of bit [31], the
265  actual use of bits in the
266  separate sub-fields of this
267  register is determined by the
268  sequencer firmware. This
269  register need only be accessed
270  when the sequencer program is
271  stored in RAM. The reset value
272  of the RESTE bit depends upon
273  the option chosen for sequencer
274  program storage. */
275 #define PKA_OPTIONS 0x440040F4 /**< PKA hardware options register
276  This register provides the host
277  with a means to determine the
278  hardware configuration
279  implemented in this PKA engine,
280  focused on options that have an
281  effect on software interacting
282  with the module. Note: (32 x
283  (1st LNME nr. of PEs + 1st LNME
284  FIFO RAM depth - 10)) equals the
285  maximum modulus vector length
286  (in bits) that can be handled by
287  the modular exponentiation and
288  ECC operations executed on a PKA
289  engine that includes an LNME. */
290 #define PKA_SW_REV 0x440040F8 /**< PKA firmware revision and
291  capabilities register This
292  register allows the host access
293  to the internal firmware
294  revision number of the PKA
295  Engine for software driver
296  matching and diagnostic
297  purposes. This register also
298  contains a field that encodes
299  the capabilities of the embedded
300  firmware. The PKA_SW_REV
301  register is written by the
302  firmware within a few clock
303  cycles after starting up that
304  firmware. The hardware reset
305  value is zero, indicating that
306  the information has not been
307  written yet. */
308 #define PKA_REVISION 0x440040FC /**< PKA hardware revision register
309  This register allows the host
310  access to the hardware revision
311  number of the PKA engine for
312  software driver matching and
313  diagnostic purposes. It is
314  always located at the highest
315  address in the access space of
316  the module and contains an
317  encoding of the EIP number (with
318  its complement as signature) for
319  recognition of the hardware
320  module. */
321 /** @} */
322 /*---------------------------------------------------------------------------*/
323 /** \name PKA_APTR register registers bit fields
324  * @{
325  */
326 #define PKA_APTR_APTR_M 0x000007FF /**< This register specifies the
327  location of vector A within the
328  PKA RAM. Vectors are identified
329  through the location of their
330  least-significant 32-bit word.
331  Note that bit [0] must be zero
332  to ensure that the vector starts
333  at an 8-byte boundary. */
334 #define PKA_APTR_APTR_S 0
335 /** @} */
336 /*---------------------------------------------------------------------------*/
337 /** \name PKA_BPTR register registers bit fields
338  * @{
339  */
340 #define PKA_BPTR_BPTR_M 0x000007FF /**< This register specifies the
341  location of vector B within the
342  PKA RAM. Vectors are identified
343  through the location of their
344  least-significant 32-bit word.
345  Note that bit [0] must be zero
346  to ensure that the vector starts
347  at an 8-byte boundary. */
348 #define PKA_BPTR_BPTR_S 0
349 /** @} */
350 /*---------------------------------------------------------------------------*/
351 /** \name PKA_CPTR register registers bit fields
352  * @{
353  */
354 #define PKA_CPTR_CPTR_M 0x000007FF /**< This register specifies the
355  location of vector C within the
356  PKA RAM. Vectors are identified
357  through the location of their
358  least-significant 32-bit word.
359  Note that bit [0] must be zero
360  to ensure that the vector starts
361  at an 8-byte boundary. */
362 #define PKA_CPTR_CPTR_S 0
363 /** @} */
364 /*---------------------------------------------------------------------------*/
365 /** \name PKA_DPTR register registers bit fields
366  * @{
367  */
368 #define PKA_DPTR_DPTR_M 0x000007FF /**< This register specifies the
369  location of vector D within the
370  PKA RAM. Vectors are identified
371  through the location of their
372  least-significant 32-bit word.
373  Note that bit [0] must be zero
374  to ensure that the vector starts
375  at an 8-byte boundary. */
376 #define PKA_DPTR_DPTR_S 0
377 /** @} */
378 /*---------------------------------------------------------------------------*/
379 /** \name PKA_ALENGTH register registers bit fields
380  * @{
381  */
382 #define PKA_ALENGTH_ALENGTH_M 0x000001FF /**< This register specifies the
383  length (in 32-bit words) of
384  Vector A. */
385 #define PKA_ALENGTH_ALENGTH_S 0
386 /** @} */
387 /*---------------------------------------------------------------------------*/
388 /** \name PKA_BLENGTH register registers bit fields
389  * @{
390  */
391 #define PKA_BLENGTH_BLENGTH_M 0x000001FF /**< This register specifies the
392  length (in 32-bit words) of
393  Vector B. */
394 #define PKA_BLENGTH_BLENGTH_S 0
395 /** @} */
396 /*---------------------------------------------------------------------------*/
397 /** \name PKA_SHIFT register registers bit fields
398  * @{
399  */
400 #define PKA_SHIFT_NUM_BITS_TO_SHIFT_M \
401  0x0000001F /**< This register specifies the
402  number of bits to shift the
403  input vector (in the range 0-31)
404  during a Rshift or Lshift
405  operation. */
406 
407 #define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0
408 /** @} */
409 /*---------------------------------------------------------------------------*/
410 /** \name PKA_FUNCTION register registers bit fields
411  * @{
412  */
413 #define PKA_FUNCTION_STALL_RESULT \
414  0x01000000 /**< When written with a 1b,
415  updating of the PKA_COMPARE,
416  PKA_MSW and PKA_DIVMSW
417  registers, as well as resetting
418  the run bit is stalled beyond
419  the point that a running
420  operation is actually finished.
421  Use this to allow software
422  enough time to read results from
423  a previous operation when the
424  newly started operation is known
425  to take only a short amount of
426  time. If a result is waiting,
427  the result registers is updated
428  and the run bit is reset in the
429  clock cycle following writing
430  the stall result bit back to 0b.
431  The Stall result function may
432  only be used for basic PKCP
433  operations. */
434 
435 #define PKA_FUNCTION_STALL_RESULT_M \
436  0x01000000
437 #define PKA_FUNCTION_STALL_RESULT_S 24
438 #define PKA_FUNCTION_RUN 0x00008000 /**< The host sets this bit to
439  instruct the PKA module to begin
440  processing the basic PKCP or
441  complex sequencer operation.
442  This bit is reset low
443  automatically when the operation
444  is complete. The complement of
445  this bit is output as
446  interrupts[1]. After a reset,
447  the run bit is always set to 1b.
448  Depending on the option, program
449  ROM or program RAM, the
450  following applies: Program ROM -
451  The first sequencer instruction
452  sets the bit to 0b. This is done
453  immediately after the hardware
454  reset is released. Program RAM -
455  The sequencer must set the bit
456  to 0b. As a valid firmware may
457  not have been loaded, the
458  sequencer is held in software
459  reset after the hardware reset
460  is released (the reset bit in
461  PKA_SEQ_CRTL is set to 1b).
462  After the FW image is loaded and
463  the Reset bit is cleared, the
464  sequencer starts to execute the
465  FW. The first instruction clears
466  the run bit. In both cases a few
467  clock cycles are needed before
468  the first instruction is
469  executed and the run bit state
470  has been propagated. */
471 #define PKA_FUNCTION_RUN_M 0x00008000
472 #define PKA_FUNCTION_RUN_S 15
473 #define PKA_FUNCTION_SEQUENCER_OPERATIONS_M \
474  0x00007000 /**< These bits select the complex
475  sequencer operation to perform:
476  000b: None 001b: ExpMod-CRT
477  010b: ExpMod-ACT4 (compatible
478  with EIP2315) 011b: ECC-ADD (if
479  available in firmware, otherwise
480  reserved) 100b: ExpMod-ACT2
481  (compatible with EIP2316) 101b:
482  ECC-MUL (if available in
483  firmware, otherwise reserved)
484  110b: ExpMod-variable 111b:
485  ModInv (if available in
486  firmware, otherwise reserved)
487  The encoding of these operations
488  is determined by sequencer
489  firmware. */
490 
491 #define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12
492 #define PKA_FUNCTION_COPY 0x00000800 /**< Perform copy operation */
493 #define PKA_FUNCTION_COPY_M 0x00000800
494 #define PKA_FUNCTION_COPY_S 11
495 #define PKA_FUNCTION_COMPARE 0x00000400 /**< Perform compare operation */
496 #define PKA_FUNCTION_COMPARE_M 0x00000400
497 #define PKA_FUNCTION_COMPARE_S 10
498 #define PKA_FUNCTION_MODULO 0x00000200 /**< Perform modulo operation */
499 #define PKA_FUNCTION_MODULO_M 0x00000200
500 #define PKA_FUNCTION_MODULO_S 9
501 #define PKA_FUNCTION_DIVIDE 0x00000100 /**< Perform divide operation */
502 #define PKA_FUNCTION_DIVIDE_M 0x00000100
503 #define PKA_FUNCTION_DIVIDE_S 8
504 #define PKA_FUNCTION_LSHIFT 0x00000080 /**< Perform left shift operation */
505 #define PKA_FUNCTION_LSHIFT_M 0x00000080
506 #define PKA_FUNCTION_LSHIFT_S 7
507 #define PKA_FUNCTION_RSHIFT 0x00000040 /**< Perform right shift operation */
508 #define PKA_FUNCTION_RSHIFT_M 0x00000040
509 #define PKA_FUNCTION_RSHIFT_S 6
510 #define PKA_FUNCTION_SUBTRACT 0x00000020 /**< Perform subtract operation */
511 #define PKA_FUNCTION_SUBTRACT_M 0x00000020
512 #define PKA_FUNCTION_SUBTRACT_S 5
513 #define PKA_FUNCTION_ADD 0x00000010 /**< Perform add operation */
514 #define PKA_FUNCTION_ADD_M 0x00000010
515 #define PKA_FUNCTION_ADD_S 4
516 #define PKA_FUNCTION_MS_ONE 0x00000008 /**< Loads the location of the Most
517  Significant one bit within the
518  result word indicated in the
519  PKA_MSW register into bits [4:0]
520  of the PKA_DIVMSW register - can
521  only be used with basic PKCP
522  operations, except for Divide,
523  Modulo and Compare. */
524 #define PKA_FUNCTION_MS_ONE_M 0x00000008
525 #define PKA_FUNCTION_MS_ONE_S 3
526 #define PKA_FUNCTION_ADDSUB 0x00000002 /**< Perform combined add/subtract
527  operation */
528 #define PKA_FUNCTION_ADDSUB_M 0x00000002
529 #define PKA_FUNCTION_ADDSUB_S 1
530 #define PKA_FUNCTION_MULTIPLY 0x00000001 /**< Perform multiply operation */
531 #define PKA_FUNCTION_MULTIPLY_M 0x00000001
532 #define PKA_FUNCTION_MULTIPLY_S 0
533 /** @} */
534 /*---------------------------------------------------------------------------*/
535 /** \name PKA_COMPARE register registers bit fields
536  * @{
537  */
538 #define PKA_COMPARE_A_GREATER_THAN_B \
539  0x00000004 /**< Vector_A is greater than
540  Vector_B */
541 
542 #define PKA_COMPARE_A_GREATER_THAN_B_M \
543  0x00000004
544 #define PKA_COMPARE_A_GREATER_THAN_B_S 2
545 #define PKA_COMPARE_A_LESS_THAN_B \
546  0x00000002 /**< Vector_A is less than Vector_B */
547 
548 #define PKA_COMPARE_A_LESS_THAN_B_M \
549  0x00000002
550 #define PKA_COMPARE_A_LESS_THAN_B_S 1
551 #define PKA_COMPARE_A_EQUALS_B 0x00000001 /**< Vector_A is equal to Vector_B */
552 #define PKA_COMPARE_A_EQUALS_B_M \
553  0x00000001
554 #define PKA_COMPARE_A_EQUALS_B_S 0
555 /** @} */
556 /*---------------------------------------------------------------------------*/
557 /** \name PKA_MSW register registers bit fields
558  * @{
559  */
560 #define PKA_MSW_RESULT_IS_ZERO 0x00008000 /**< The result vector is all
561  zeroes, ignore the address
562  returned in bits [10:0] */
563 #define PKA_MSW_RESULT_IS_ZERO_M \
564  0x00008000
565 #define PKA_MSW_RESULT_IS_ZERO_S 15
566 #define PKA_MSW_MSW_ADDRESS_M 0x000007FF /**< Address of the most-significant
567  nonzero 32-bit word of the
568  result vector in PKA RAM */
569 #define PKA_MSW_MSW_ADDRESS_S 0
570 /** @} */
571 /*---------------------------------------------------------------------------*/
572 /** \name PKA_DIVMSW register registers bit fields
573  * @{
574  */
575 #define PKA_DIVMSW_RESULT_IS_ZERO \
576  0x00008000 /**< The result vector is all
577  zeroes, ignore the address
578  returned in bits [10:0] */
579 
580 #define PKA_DIVMSW_RESULT_IS_ZERO_M \
581  0x00008000
582 #define PKA_DIVMSW_RESULT_IS_ZERO_S 15
583 #define PKA_DIVMSW_MSW_ADDRESS_M \
584  0x000007FF /**< Address of the most significant
585  nonzero 32-bit word of the
586  remainder result vector in PKA
587  RAM */
588 
589 #define PKA_DIVMSW_MSW_ADDRESS_S 0
590 /** @} */
591 /*---------------------------------------------------------------------------*/
592 /** \name PKA_SEQ_CTRL register registers bit fields
593  * @{
594  */
595 #define PKA_SEQ_CTRL_RESET 0x80000000 /**< Option program ROM: Reset value
596  = 0. Read/Write, reset value 0b
597  (ZERO). Writing 1b resets the
598  sequencer, write to 0b to
599  restart operations again. As the
600  reset value is 0b, the sequencer
601  will automatically start
602  operations executing from
603  program ROM. This bit should
604  always be written with zero and
605  ignored when reading this
606  register. Option Program RAM:
607  Reset value =1. Read/Write,
608  reset value 1b (ONE). When 1b,
609  the sequencer is held in a reset
610  state and the PKA_PROGRAM area
611  is accessible for loading the
612  sequencer program (while the
613  PKA_DATA_RAM is inaccessible),
614  write to 0b to (re)start
615  sequencer operations and disable
616  PKA_PROGRAM area accessibility
617  (also enables the PKA_DATA_RAM
618  accesses). Resetting the
619  sequencer (in order to load
620  other firmware) should only be
621  done when the PKA Engine is not
622  performing any operations (i.e.
623  the run bit in the PKA_FUNCTION
624  register should be zero). */
625 #define PKA_SEQ_CTRL_RESET_M 0x80000000
626 #define PKA_SEQ_CTRL_RESET_S 31
627 #define PKA_SEQ_CTRL_SEQUENCER_STATUS_M \
628  0x0000FF00 /**< These read-only bits can be
629  used by the sequencer to
630  communicate status to the
631  outside world. Bit [8] is also
632  used as sequencer interrupt,
633  with the complement of this bit
634  ORed into the run bit in
635  PKA_FUNCTION. This field should
636  always be written with zeroes
637  and ignored when reading this
638  register. */
639 
640 #define PKA_SEQ_CTRL_SEQUENCER_STATUS_S 8
641 #define PKA_SEQ_CTRL_SW_CONTROL_STATUS_M \
642  0x000000FF /**< These bits can be used by
643  software to trigger sequencer
644  operations. External logic can
645  set these bits by writing 1b,
646  cannot reset them by writing 0b.
647  The sequencer can reset these
648  bits by writing 0b, cannot set
649  them by writing 1b. Setting the
650  run bit in PKA_FUNCTION together
651  with a nonzero sequencer
652  operations field automatically
653  sets bit [0] here. This field
654  should always be written with
655  zeroes and ignored when reading
656  this register. */
657 
658 #define PKA_SEQ_CTRL_SW_CONTROL_STATUS_S 0
659 /** @} */
660 /*---------------------------------------------------------------------------*/
661 /** \name PKA_OPTIONS register registers bit fields
662  * @{
663  */
664 #define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M \
665  0xFF000000 /**< Number of words in the first
666  LNME's FIFO RAM Should be
667  ignored if LNME configuration is
668  0. The contents of this field
669  indicate the actual depth as
670  selected by the LNME FIFO RAM
671  size strap input, fifo_size_sel.
672  Note: Reset value is undefined */
673 
674 #define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_S 24
675 #define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M \
676  0x003F0000 /**< Number of processing elements
677  in the pipeline of the first
678  LNME Should be ignored if LNME
679  configuration is 0. Note: Reset
680  value is undefined. */
681 
682 #define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_S 16
683 #define PKA_OPTIONS_MMM3A 0x00001000 /**< Reserved for a future
684  functional extension to the LNME
685  Always 0b */
686 #define PKA_OPTIONS_MMM3A_M 0x00001000
687 #define PKA_OPTIONS_MMM3A_S 12
688 #define PKA_OPTIONS_INT_MASKING 0x00000800 /**< Value 0b indicates that the
689  main interrupt output (bit [1]
690  of the interrupts output bus) is
691  the direct complement of the run
692  bit in the PKA_CONTROL register,
693  value 1b indicates that
694  interrupt masking logic is
695  present for this output. Note:
696  Reset value is undefined */
697 #define PKA_OPTIONS_INT_MASKING_M \
698  0x00000800
699 #define PKA_OPTIONS_INT_MASKING_S 11
700 #define PKA_OPTIONS_PROTECTION_OPTION_M \
701  0x00000700 /**< Value 0 indicates no additional
702  protection against side channel
703  attacks, value 1 indicates the
704  SCAP option, value 3 indicates
705  the PROT option; other values
706  are reserved. Note: Reset value
707  is undefined */
708 
709 #define PKA_OPTIONS_PROTECTION_OPTION_S 8
710 #define PKA_OPTIONS_PROGRAM_RAM 0x00000080 /**< Value 1b indicates sequencer
711  program storage in RAM, value 0b
712  in ROM. Note: Reset value is
713  undefined */
714 #define PKA_OPTIONS_PROGRAM_RAM_M \
715  0x00000080
716 #define PKA_OPTIONS_PROGRAM_RAM_S 7
717 #define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M \
718  0x00000060 /**< Value 1 indicates a standard
719  sequencer; other values are
720  reserved. */
721 
722 #define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5
723 #define PKA_OPTIONS_LNME_CONFIGURATION_M \
724  0x0000001C /**< Value 0 indicates NO LNME,
725  value 1 indicates one standard
726  LNME (with alpha = 32, beta =
727  8); other values reserved. Note:
728  Reset value is undefined */
729 
730 #define PKA_OPTIONS_LNME_CONFIGURATION_S 2
731 #define PKA_OPTIONS_PKCP_CONFIGURATION_M \
732  0x00000003 /**< Value 1 indicates a PKCP with a
733  16x16 multiplier, value 2
734  indicates a PKCP with a 32x32
735  multiplier, other values
736  reserved. Note: Reset value is
737  undefined. */
738 
739 #define PKA_OPTIONS_PKCP_CONFIGURATION_S 0
740 /** @} */
741 /*---------------------------------------------------------------------------*/
742 /** \name PKA_SW_REV register registers bit fields
743  * @{
744  */
745 #define PKA_SW_REV_FW_CAPABILITIES_M \
746  0xF0000000 /**< 4-bit binary encoding for the
747  functionality implemented in the
748  firmware. Value 0 indicates
749  basic ModExp with/without CRT.
750  Value 1 adds Modular Inversion,
751  value 2 adds Modular Inversion
752  and ECC operations. Values 3-15
753  are reserved. */
754 
755 #define PKA_SW_REV_FW_CAPABILITIES_S 28
756 #define PKA_SW_REV_MAJOR_FW_REVISION_M \
757  0x0F000000 /**< 4-bit binary encoding of the
758  major firmware revision number */
759 
760 #define PKA_SW_REV_MAJOR_FW_REVISION_S 24
761 #define PKA_SW_REV_MINOR_FW_REVISION_M \
762  0x00F00000 /**< 4-bit binary encoding of the
763  minor firmware revision number */
764 
765 #define PKA_SW_REV_MINOR_FW_REVISION_S 20
766 #define PKA_SW_REV_FW_PATCH_LEVEL_M \
767  0x000F0000 /**< 4-bit binary encoding of the
768  firmware patch level, initial
769  release will carry value zero
770  Patches are used to remove bugs
771  without changing the
772  functionality or interface of a
773  module. */
774 
775 #define PKA_SW_REV_FW_PATCH_LEVEL_S 16
776 /** @} */
777 /*---------------------------------------------------------------------------*/
778 /** \name PKA_REVISION register registers bit fields
779  * @{
780  */
781 #define PKA_REVISION_MAJOR_HW_REVISION_M \
782  0x0F000000 /**< 4-bit binary encoding of the
783  major hardware revision number */
784 
785 #define PKA_REVISION_MAJOR_HW_REVISION_S 24
786 #define PKA_REVISION_MINOR_HW_REVISION_M \
787  0x00F00000 /**< 4-bit binary encoding of the
788  minor hardware revision number */
789 
790 #define PKA_REVISION_MINOR_HW_REVISION_S 20
791 #define PKA_REVISION_HW_PATCH_LEVEL_M \
792  0x000F0000 /**< 4-bit binary encoding of the
793  hardware patch level, initial
794  release will carry value zero
795  Patches are used to remove bugs
796  without changing the
797  functionality or interface of a
798  module. */
799 
800 #define PKA_REVISION_HW_PATCH_LEVEL_S 16
801 #define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_M \
802  0x0000FF00 /**< Bit-by-bit logic complement of
803  bits [7:0], EIP-28 gives 0xE3 */
804 
805 #define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8
806 #define PKA_REVISION_BASIC_EIP_NUMBER_M \
807  0x000000FF /**< 8-bit binary encoding of the
808  EIP number, EIP-28 gives 0x1C */
809 
810 #define PKA_REVISION_BASIC_EIP_NUMBER_S 0
811 
812 /** @} */
813 /*---------------------------------------------------------------------------*/
814 /** \name PKA driver return codes
815  * @{
816  */
817 #define PKA_STATUS_SUCCESS 0 /**< Success */
818 #define PKA_STATUS_FAILURE 1 /**< Failure */
819 #define PKA_STATUS_INVALID_PARAM 2 /**< Invalid parameter */
820 #define PKA_STATUS_BUF_UNDERFLOW 3 /**< Buffer underflow */
821 #define PKA_STATUS_RESULT_0 4 /**< Result is all zeros */
822 #define PKA_STATUS_A_GR_B 5 /**< Big number compare return status if
823  the first big num is greater than
824  the second. */
825 #define PKA_STATUS_A_LT_B 6 /**< Big number compare return status if
826  the first big num is less than the
827  second. */
828 #define PKA_STATUS_OPERATION_INPRG 7 /**< PKA operation is in progress. */
829 #define PKA_STATUS_OPERATION_NOT_INPRG 8 /**< No PKA operation is in progress. */
830 #define PKA_STATUS_SIGNATURE_INVALID 9 /**< Signature is invalid. */
831 
832 /** @} */
833 /*---------------------------------------------------------------------------*/
834 /** \name PKA functions
835  * @{
836  */
837 
838 /** \brief Enables and resets the PKA engine
839  */
840 void pka_init(void);
841 
842 /** \brief Enables the PKA engine
843  */
844 void pka_enable(void);
845 
846 /** \brief Disables the PKA engine
847  * \note Call this function to save power when the engine is unused.
848  */
849 void pka_disable(void);
850 
851 /** \brief Checks the status of the PKA engine operation
852  * \retval false Result not yet available, and no error occurred
853  * \retval true Result available, or error occurred
854  */
855 uint8_t pka_check_status(void);
856 
857 /** \brief Registers a process to be notified of the completion of a PKA
858  * operation
859  * \param p Process to be polled upon IRQ
860  * \note This function is only supposed to be called by the PKA drivers.
861  */
862 void pka_register_process_notification(struct process *p);
863 
864 /** @} */
865 
866 #endif /* PKA_H_ */
867 
868 /**
869  * @}
870  * @}
871  */
pka_init
void pka_init(void)
Enables and resets the PKA engine.
Definition: pka.c:85
pka_disable
void pka_disable(void)
Disables the PKA engine.
Definition: pka.c:110
pka_register_process_notification
void pka_register_process_notification(struct process *p)
Registers a process to be notified of the completion of a PKA operation.
Definition: pka.c:124
pka_check_status
uint8_t pka_check_status(void)
Checks the status of the PKA engine operation.
Definition: pka.c:119
pka_enable
void pka_enable(void)
Enables the PKA engine.
Definition: pka.c:101
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