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platform-conf.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /**
31  * \file
32  * Platform configuration for the wismote platform.
33  */
34 
35 #ifndef PLATFORM_CONF_H_
36 #define PLATFORM_CONF_H_
37 
38 /*
39  * Definitions below are dictated by the hardware and not really
40  * changeable!
41  */
42 
43 #define PLATFORM_HAS_LEDS 1
44 #define PLATFORM_HAS_BUTTON 1
45 
46 /* CPU target speed in Hz */
47 #define F_CPU 16000000uL
48 
49 /* Our clock resolution, this is the same as Unix HZ. */
50 #define CLOCK_CONF_SECOND 128UL
51 #define RTIMER_CONF_SECOND (4096U*8)
52 
53 #define BAUD2UBR(baud) (baud)
54 
55 #define CCIF
56 #define CLIF
57 
58 #define HAVE_STDINT_H
59 #include "msp430def.h"
60 
61 
62 /* Types for clocks and uip_stats */
63 typedef unsigned short uip_stats_t;
64 typedef unsigned long clock_time_t;
65 typedef unsigned long off_t;
66 
67 /* the low-level radio driver */
68 #define NETSTACK_CONF_RADIO cc2520_driver
69 
70 #define ROM_ERASE_UNIT_SIZE 512
71 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
72 
73 
74 #define CFS_CONF_OFFSET_TYPE long
75 
76 
77 /* Use the first 64k of external flash for node configuration */
78 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
79 
80 /* Use the second 64k of external flash for codeprop. */
81 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
82 
83 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
84 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
85 
86 #define CFS_RAM_CONF_SIZE 4096
87 
88 /*
89  * SPI bus configuration for the wismote
90  */
91 
92 /* SPI input/output registers. */
93 #define SPI_TXBUF UCB0TXBUF
94 #define SPI_RXBUF UCB0RXBUF
95 
96  /* USART0 Tx ready? */
97 #define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0)
98  /* USART0 Rx ready? */
99 #define SPI_WAITFOREORx() while ((UCB0IFG & UCRXIFG) == 0)
100  /* USART0 Tx buffer ready? */
101 #define SPI_WAITFORTxREADY() while ((UCB0IFG & UCTXIFG) == 0)
102 /* /\* USART0 Tx ready? *\/ */
103 /* #define SPI_WAITFOREOTx() while (!(UCB0IFG & UCRXIFG)) */
104 /* /\* USART0 Rx ready? *\/ */
105 /* #define SPI_WAITFOREORx() while (!(UCB0IFG & UCRXIFG)) */
106 /* /\* USART0 Tx buffer ready? *\/ */
107 /* #define SPI_WAITFORTxREADY() while (!(UCB0IFG & UCRXIFG)) */
108 /* #define SPI_BUSY_WAIT() while ((UCB0STAT & UCBUSY) == 1) */
109 
110 #define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
111 #define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
112 #define SCK 3 /* P3.3 - Output: SPI Serial Clock (SCLK) */
113 /* #define SCK 1 /\* P3.1 - Output: SPI Serial Clock (SCLK) *\/ */
114 /* #define MOSI 2 /\* P3.2 - Output: SPI Master out - slave in (MOSI) *\/ */
115 /* #define MISO 3 /\* P3.3 - Input: SPI Master in - slave out (MISO) *\/ */
116 
117 /*
118  * SPI bus - M25P80 external flash configuration.
119  */
120 
121 #define FLASH_PWR //3 /* P4.3 Output */
122 #define FLASH_CS //4 /* P4.4 Output */
123 #define FLASH_HOLD //7 /* P4.7 Output */
124 
125 /* Enable/disable flash access to the SPI bus (active low). */
126 
127  /* ENABLE CSn (active low) */
128 #define SPI_FLASH_ENABLE() do{ UCB0CTL1 &= ~UCSWRST; clock_delay(5); P4OUT &= ~BIT0;clock_delay(5);}while(0)
129  /* DISABLE CSn (active low) */
130 #define SPI_FLASH_DISABLE() do{clock_delay(5);UCB0CTL1 |= UCSWRST;clock_delay(1); P4OUT |= BIT0;clock_delay(5);}while(0)
131 
132 #define SPI_FLASH_HOLD() // ( P4OUT &= ~BV(FLASH_HOLD) )
133 #define SPI_FLASH_UNHOLD() //( P4OUT |= BV(FLASH_HOLD) )
134 
135 /*
136  * SPI bus - CC2520 pin configuration.
137  */
138 
139 #define CC2520_CONF_SYMBOL_LOOP_COUNT 2604 /* 326us msp430X @ 16MHz */
140 
141 /* P1.6 - Input: FIFOP from CC2520 */
142 #define CC2520_FIFOP_PORT(type) P1##type
143 #define CC2520_FIFOP_PIN 6
144 /* P1.5 - Input: FIFO from CC2520 */
145 #define CC2520_FIFO_PORT(type) P1##type
146 #define CC2520_FIFO_PIN 5
147 /* P1.7 - Input: CCA from CC2520 */
148 #define CC2520_CCA_PORT(type) P1##type
149 #define CC2520_CCA_PIN 7
150 /* P2.0 - Input: SFD from CC2520 */
151 #define CC2520_SFD_PORT(type) P2##type
152 #define CC2520_SFD_PIN 0
153 /* P3.0 - Output: SPI Chip Select (CS_N) */
154 #define CC2520_CSN_PORT(type) P3##type
155 #define CC2520_CSN_PIN 0
156 /* P4.3 - Output: VREG_EN to CC2520 */
157 #define CC2520_VREG_PORT(type) P4##type
158 #define CC2520_VREG_PIN 3
159 /* P4.4 - Output: RESET_N to CC2520 */
160 #define CC2520_RESET_PORT(type) P4##type
161 #define CC2520_RESET_PIN 4
162 
163 #define CC2520_IRQ_VECTOR PORT1_VECTOR
164 
165 /* Pin status.CC2520 */
166 #define CC2520_FIFOP_IS_1 (!!(CC2520_FIFOP_PORT(IN) & BV(CC2520_FIFOP_PIN)))
167 #define CC2520_FIFO_IS_1 (!!(CC2520_FIFO_PORT(IN) & BV(CC2520_FIFO_PIN)))
168 #define CC2520_CCA_IS_1 (!!(CC2520_CCA_PORT(IN) & BV(CC2520_CCA_PIN)))
169 #define CC2520_SFD_IS_1 (!!(CC2520_SFD_PORT(IN) & BV(CC2520_SFD_PIN)))
170 
171 /* The CC2520 reset pin. */
172 #define SET_RESET_INACTIVE() (CC2520_RESET_PORT(OUT) |= BV(CC2520_RESET_PIN))
173 #define SET_RESET_ACTIVE() (CC2520_RESET_PORT(OUT) &= ~BV(CC2520_RESET_PIN))
174 
175 /* CC2520 voltage regulator enable pin. */
176 #define SET_VREG_ACTIVE() (CC2520_VREG_PORT(OUT) |= BV(CC2520_VREG_PIN))
177 #define SET_VREG_INACTIVE() (CC2520_VREG_PORT(OUT) &= ~BV(CC2520_VREG_PIN))
178 
179 /* CC2520 rising edge trigger for external interrupt 0 (FIFOP). */
180 #define CC2520_FIFOP_INT_INIT() do { \
181  CC2520_FIFOP_PORT(IES) &= ~BV(CC2520_FIFOP_PIN); \
182  CC2520_CLEAR_FIFOP_INT(); \
183  } while(0)
184 
185 /* FIFOP on external interrupt 0. */
186 /* FIFOP on external interrupt 0. */
187 #define CC2520_ENABLE_FIFOP_INT() do { P1IE |= BV(CC2520_FIFOP_PIN); } while (0)
188 #define CC2520_DISABLE_FIFOP_INT() do { P1IE &= ~BV(CC2520_FIFOP_PIN); } while (0)
189 #define CC2520_CLEAR_FIFOP_INT() do { P1IFG &= ~BV(CC2520_FIFOP_PIN); } while (0)
190 
191 /*
192  * Enables/disables CC2520 access to the SPI bus (not the bus).
193  * (Chip Select)
194  */
195 
196  /* ENABLE CSn (active low) */
197 #define CC2520_SPI_ENABLE() do{ UCB0CTL1 &= ~UCSWRST; clock_delay(5); P3OUT &= ~BIT0;clock_delay(5);}while(0)
198  /* DISABLE CSn (active low) */
199 #define CC2520_SPI_DISABLE() do{clock_delay(5);UCB0CTL1 |= UCSWRST;clock_delay(1); P3OUT |= BIT0;clock_delay(5);}while(0)
200 #define CC2520_SPI_IS_ENABLED() ((CC2520_CSN_PORT(OUT) & BV(CC2520_CSN_PIN)) != BV(CC2520_CSN_PIN))
201 
202 #endif /* PLATFORM_CONF_H_ */
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