Contiki 3.x
serial.c
1 /*-----------------------------------------------------------------------------------------------------------------------------------*/
2 /* serial.c
3  *
4  * Initialisation & Commands for Serial communication on the Freescale FRDM-KL25z Freedom Board
5  *
6  * Author: Graeme Bragg
7  * ARM-ECS / Pervasive Systems Centre
8  * School of Electronics & Computer Science
9  * University of Southampton
10  *
11  *
12  * 25/2/2013 Rev.01 Includes functions for UART0 ONLY. Configured to
13  * function on PTA1 and PTA2. Configured for 38400 8 N 1.
14  * Configured to run from MCGFLLCLK @ 20.97152MHz. Uses
15  * Interrupt for RX, does NOT use interrupt for TX.
16  * 7/3/2013 Rev.02 Modified UART0 IRQ to use a Callback if one is registered.
17  * 12/3/2013 Rev.03 Enabled dynamic baud rate setting.
18  * 5/2/2014 Rev.04 Added code for UART1 and UART2. Still static pin mappings.
19  * 11/2/2014 Rev.05
20  *
21  *
22  * Page references relate to the KL25 Sub-Family Reference Manual, Document
23  * No. KL25P80M48SF0RM, Rev. 3 September 2012. Available on 25/02/2013 from:
24  * http://cache.freescale.com/files/32bit/doc/ref_manual/KL25P80M48SF0RM.pdf?fr=gdc
25  *
26  * Page references to "M0 Book" refer to "The Definitive Guide to the
27  * ARM Cortex-M0" by Joseph Yiu, ISBN 978-0-12-385477-3.
28  *
29  *
30  * ***NB*** This file is intended for use with a new "Bareboard"
31  * project (with norapid-development) in Code Warrior.
32  * If this is not the case, you MUST ensure that an
33  * appropriate entry of "UART0_IRQHandler" exists in
34  * entry 28 (address 0x00000070) of the VectorTable.
35  *
36  * Appropriate entries for the interrupt handler exist
37  * in the vector table contained in the generated
38  * kinetis_sysinit.c file
39  *
40  *
41  * Copyright (c) 2014, University of Southampton, Electronics and Computer Science
42  * All rights reserved.
43  *
44  * Redistribution and use in source and binary forms, with or without
45  * modification, are permitted provided that the following conditions
46  * are met:
47  * 1. Redistributions of source code must retain the above copyright
48  * notice, this list of conditions and the following disclaimer.
49  * 2. Redistributions in binary form must reproduce the above copyright
50  * notice, this list of conditions and the following disclaimer in the
51  * documentation and/or other materials provided with the distribution.
52  * 3. Neither the name of the Institute nor the names of its contributors
53  * may be used to endorse or promote products derived from this software
54  * without specific prior written permission.
55  *
56  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
57  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
59  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
60  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
61  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
62  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66  * SUCH DAMAGE.
67  *
68  */
69 /*-----------------------------------------------------------------------------------------------------------------------------------*/
70 
71 #include <stdlib.h>
72 #include <stdio.h>
73 #include <MKL25Z4.h> /* I/O map for MKL25Z128VLK4 */
74 #include "nvic.h"
75 #include "serial.h"
76 #include "cpu.h"
77 
78 /* Baud Rate is set using a combination of the Baud Rate Divider and Over Sampling Ratio. */
79 /* BRD of 0x22 and OSR of 0x0F give a baud rate of 38550.5882 which functions with 38400. */
80 #define UART0_OSR 0x0F
81 
82 /*-----------------------------------------------------------------------------------------------------------------------------------*/
83 /*-------------------------------------------------------- Local Definitions --------------------------------------------------------*/
84 
85 /* Register Mask definitions. Other used definitions are defined in MKL25Z4.h */
86 #define UART_C2_TeRe 0x0C /* UART C2 register Transmitter & Receiver enable mask. */
87 #define UART_S1_Err 0x0F /* UART S1 status register error mask. */
88 
89 /*--------------------------------------------------------- End Definitions ---------------------------------------------------------*/
90 /*-----------------------------------------------------------------------------------------------------------------------------------*/
91 
92 static void (*UART0_callback)(char);
93 static void (*UART1_callback)(char);
94 static void (*UART2_callback)(char);
95 
96 
97 /*-----------------------------------------------------------------------------------------------------------------------------------*/
98 /* Initialisation Functions */
99 
100 void serial_init(uint32_t UART0_baudrate, uint32_t UART1_baudrate, uint32_t UART2_baudrate) /* Initialise Serial port(s). */
101 {
102  UART0_init(UART0_baudrate);
103  UART1_init(UART1_baudrate);
104  UART2_init(UART2_baudrate);
105 }
106 
107 
108 void UART0_init(uint32_t baudrate) /* Initialise UART0. */
109 {
110  if(baudrate != 0)
111  {
112  uint16_t bauddiv;
113 
114  /* Configure Clocking for UART0 */
115  SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* SIM_SCGC4: System Clock Gate Register 4, Page 204. UART0=1 */
116  SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) | 0x04000000); /* SIM_SOPT2: Set UART0 Clock Source, Page 195. UART0SRC=1 */
117 
118  /* Configure pins: PTA1 as RX, PTA2 as TX */
119  PORTA_PCR1 |= 0x205; /* PORTA_PCR2: PortA, Pin2 Control Register, Page 183. Sets PTA1 pin as UART0_RX */
120  PORTA_PCR2 |= 0x205; /* PORTA_PCR2: PortA, Pin2 Control Register, Page 183. Sets PTA2 pin as UART0_TX */
121 
122  /* Configure Interrupt Controller for UART0 */
123  NVIC_Set_Priority(IRQ_UART0, 0x80); /* Set UART0 priority to 2. */
124  NVIC_ENABLE_INT(IRQ_UART0); /* Enable UART0 NVIC Interrupt. */
125  UART0_callback = NULL; /* Set Callback to NULL */
126 
127  //NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~0x7F) | (uint32_t)0x80); /* Set NVIC_IPR3: Irq 12 to 15 Priority Register. PRI_12=0x80. */
128  //NVIC_ISER |= 0x1000; /* Set NVIC_ISER: Irq 0 to 31 Set-Enable Register. SETENA|=0x1000. */
129 
130 
131  /* Configure UART0 Registers */
132  //Clear control registers to ensure reset state.
133  UART0_C2 = 0x00; /* Clear UART0_C2: Disable TX/RX for update of settings, disable interrupts. Page 728. */
134  UART0_C1 = 0x00; /* Clear UART0_C1: Enable in wait mode & disable loop mode. Page 726. */
135  UART0_C3 = 0x00; /* Clear UART0_C3: disable transmit inversion & interrupts. Page 733. */
136  UART0_C4 = 0x00; /* Clear UART0_C4: Disable Match Address Mode & clear OSR. Page 736. */
137  UART0_C5 = 0x00; /* Clear UART0_C5: disable DMA & both-edge sampling. Page 737. */
138  UART0_BDH = 0x00; /* Clear UART0_BDH: Disable other interrupts. Page 725. */
139  UART0_MA1 = 0x00; /* Clear UART0_MA1: Match Address Register 1, only used if MAEN1 in UART0_C4, Page 735. MA=0. */
140  UART0_MA2 = 0x00; /* Clear UART0_MA2: Match Address Register 2, only used if MAEN2 in UART0_C4, Page 736. MA=0. */
141 
142  //Configure Baud Rate, 8 data bits, no parity and 1 stop bit
143  bauddiv = CORECLK / ((UART0_OSR + 1) * baudrate); /* Calculate Baud Rate divisor. BR = BCLK / ((OSR +1) * BRD). Page 726. */
144  UART0_BDL = (uint8_t)(bauddiv & 0x00FF); /* Set UART0_BDL: lower Baud Rate Divisor. Page 725. */
145  UART0_BDH |= (uint8_t)((bauddiv >> 8) & 0x001F); /* Set UART0_BDH: upper Baud Rate Divisor. Page 725. */
146  UART0_C4 = (UART0_C4 & ~UART0_C4_OSR_MASK) | ((UART0_OSR) & 0x1F); /* Set UART0_C4: oversampling rate. Page 736. */
147  UART0_C1 &= ~(UART0_C1_M_MASK); /* Set UART0_C1: 8 data bits. Page 726. */
148  UART0_C1 &= ~(UART0_C1_PE_MASK); /* Set UART0_C1: no parity. Page 726. */
149  UART0_BDH &= ~(UART0_BDH_SBNS_MASK); /* Set UART0_BDH: 1 stop bit. Page 725. */
150  if ( 4 <= UART0_OSR && UART0_OSR <= 7) /* If OSR is between 4 and 7 */
151  {
152  UART0_C5 |= UART0_C5_BOTHEDGE_MASK; /* enable both edge receive sampling as per Page 737. */
153  }
154 
155  // Clear status Registers
156  UART0_S1 |= (uint8_t)(UART_S1_IDLE_MASK | UART_S1_Err); /* UART0_S1: Set UART0 Status Register S1, Page 729. IDLE=1,OR=1,NF=1,FE=1,PF=1. */
157  UART0_S2 = (uint8_t)0x00; /* UART0_S2: Set UART0 Status Register S2, Page 729. LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0. */
158 
159  //Enable the Transmitter & Receiver after UART0 settings update
160  UART0_C2 |= (uint8_t)UART_C2_TeRe; /* UART0_C2: Enable TX/RX, Page 728. TIE=0,TCIE=0,RIE=0,ILIE=0,TE=1,RE=1,RWU=0,SBK=0. */
161  }
162 }
163 
164 void UART1_init(uint32_t baudrate) /* Initialise UART1. */
165 {
166  if(baudrate != 0)
167  {
168  uint16_t bauddiv;
169 
170  /* Configure Clocking for UART0 */
171  SIM_SCGC4 |= SIM_SCGC4_UART1_MASK; /* SIM_SCGC4: System Clock Gate Register 4, Page 204. UART1=1 */
172 
173  /* Configure pins: PTE1 as RX, PTE0 as TX */
174  PORTE_PCR1 |= 0x300;
175  PORTE_PCR0 |= 0x300;
176 
177  /* Configure Interrupt Controller for UART1 */
178  NVIC_Set_Priority(IRQ_UART1, 0x80); /* Set UART1 priority to 2. */
179  NVIC_ENABLE_INT(IRQ_UART1); /* Enable UART1 NVIC Interrupt. */
180  UART1_callback = NULL; /* Set Callback to NULL */
181 
182  //NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(NVIC_IP_PRI_13(0x7F))) | (uint32_t)(NVIC_IP_PRI_13(0x80)));
183  //NVIC_ISER |= 0x2000;
184 
185 
186  /* Configure UART1 Registers */
187  //Clear control registers to ensure reset state.
188  UART1_C2 = 0x00; /* Clear UART1_C2: Disable TX/RX for update of settings, disable interrupts. Page 753. */
189  UART1_C1 = 0x00; /* Clear UART1_C1: Enable in wait mode & disable loop mode. Page 752. */
190  UART1_C3 = 0x00; /* Clear UART1_C3: disable transmit inversion & interrupts. Page 758. */
191  UART1_C4 = 0x00; /* Clear UART1_C4: Disable Match Address Mode & clear OSR. Page 760. */
192  UART1_BDH = 0x00; /* Clear UART1_BDH: Disable other interrupts. Page 751. */
193  UART1_BDL = 0x00; /* Clear UART1_BDL: Commit BDH changes. Page 751. */
194 
195  //Configure Baud Rate, 8 data bits, no parity and 1 stop bit
196  bauddiv = BUSCLK / baudrate; /* Calculate Baud Rate divisor. BR = BCLK / BRD. Page 762. */
197  UART1_BDH = (uint8_t)((bauddiv >> 8) & 0x001F); /* Set UART1_BDH: upper Baud Rate Divisor. Page 751. */
198  UART1_BDL = (uint8_t)(bauddiv & 0x00FF); /* Set UART1_BDL: lower Baud Rate Divisor. Page 751. */
199 
200 
201  // Clear status Registers
202  /* UART1_S1: No writes needed to clear. Page 755. */
203  UART1_S2 = (uint8_t)0x00; /* UART1_S2: Set UART1 Status Register S2, Page 756. */
204 
205  //Enable the Transmitter & Receiver after UART0 settings update
206  UART1_C2 |= (uint8_t)UART_C2_TeRe; /* UART1_C2: Enable TX/RX, Page 753. TIE=0,TCIE=0,RIE=0,ILIE=0,TE=1,RE=1,RWU=0,SBK=0. */
207  }
208 }
209 
210 void UART2_init(uint32_t baudrate) /* Initialise UART1. */
211 {
212  if(baudrate != 0)
213  {
214  uint16_t bauddiv;
215 
216  /* Configure Clocking for UART0 */
217  SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; /* SIM_SCGC4: System Clock Gate Register 4, Page 204. UART1=1 */
218 
219  /* Configure pins: PTE23 as RX, PTE22 as TX */
220  PORTE_PCR23 |= 0x400;
221  PORTE_PCR22 |= 0x400;
222 
223  /* Configure Interrupt Controller for UART2 */
224  NVIC_Set_Priority(IRQ_UART2, 0x80); /* Set UART2 priority to 2. */
225  NVIC_ENABLE_INT(IRQ_UART2); /* Enable UART2 NVIC Interrupt. */
226  UART2_callback = NULL; /* Set Callback to NULL */
227 
228  //NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(NVIC_IP_PRI_14(0x7F))) | (uint32_t)(NVIC_IP_PRI_14(0x80)));
229  //NVIC_ISER |= 0x4000;
230 
231  /* Configure UART1 Registers */
232  //Clear control registers to ensure reset state.
233  UART2_C2 = 0x00; /* Clear UART2_C2: Disable TX/RX for update of settings, disable interrupts. Page 753. */
234  UART2_C1 = 0x00; /* Clear UART2_C1: Enable in wait mode & disable loop mode. Page 752. */
235  UART2_C3 = 0x00; /* Clear UART2_C3: disable transmit inversion & interrupts. Page 758. */
236  UART2_C4 = 0x00; /* Clear UART2_C4: Disable Match Address Mode & clear OSR. Page 760. */
237  UART2_BDH = 0x00; /* Clear UART2_BDH: Disable other interrupts. Page 751. */
238  UART2_BDL = 0x00; /* Clear UART2_BDL: Commit BDH changes. Page 751. */
239 
240  //Configure Baud Rate, 8 data bits, no parity and 1 stop bit
241  bauddiv = BUSCLK / baudrate; /* Calculate Baud Rate divisor. BR = BCLK / BRD. Page 762. */
242  UART2_BDH = (uint8_t)((bauddiv >> 8) & 0x001F); /* Set UART2_BDH: upper Baud Rate Divisor. Page 751. */
243  UART2_BDL = (uint8_t)(bauddiv & 0x00FF); /* Set UART2_BDL: lower Baud Rate Divisor. Page 751. */
244 
245 
246  // Clear status Registers
247  /* UART1_S1: No writes needed to clear. Page 755. */
248  UART2_S2 = (uint8_t)0x00; /* UART1_S2: Set UART1 Status Register S2, Page 756. */
249 
250  //Enable the Transmitter & Receiver after UART0 settings update
251  UART2_C2 |= (uint8_t)UART_C2_TeRe; /* UART1_C2: Enable TX/RX, Page 753. TIE=0,TCIE=0,RIE=0,ILIE=0,TE=1,RE=1,RWU=0,SBK=0. */
252  }
253 }
254 
255 void UART0_reg_callback(void* UART0_Callback_Ptr) /* Register a callback function for use in UART0_IRQHandler. */
256 {
257  UART0_callback = UART0_Callback_Ptr;
258 }
259 
260 void UART1_reg_callback(void* UART1_Callback_Ptr) /* Register a callback function for use in UART0_IRQHandler. */
261 {
262  UART1_callback = UART1_Callback_Ptr;
263 }
264 
265 void UART2_reg_callback(void* UART2_Callback_Ptr) /* Register a callback function for use in UART0_IRQHandler. */
266 {
267  UART2_callback = UART2_Callback_Ptr;
268 }
269 
270 
271 /*-----------------------------------------------------------------------------------------------------------------------------------*/
272 /* Serial Functions */
273 void UART_PutChar(uint8_t uart, char outchar)
274 {
275  switch (uart){
276  case 0: UART0_PutChar(outchar);
277  break;
278  case 1: UART1_PutChar(outchar);
279  break;
280  case 2: UART2_PutChar(outchar);
281  break;
282  default:
283  break;
284  }
285 }
286 
287 void UART0_PutChar(char outChar) /* Put single character into UART0 output register */
288 {
289  while(!(UART0_S1 & UART_S1_TDRE_MASK)); /* Check for space in TX Buffer, checking TDRE bit in UART0_S1. Page 729. */
290  //while((UART0_S1 & 0x80) != 0x80);
291  UART0_D = (uint8_t)outChar; /* Write char to UART0 Data buffer. Page 734. */
292 }
293 
294 void UART1_PutChar(char outChar) /* Put single character into UART1 output register */
295 {
296  while(!(UART1_S1 & UART_S1_TDRE_MASK)); /* Check for space in TX Buffer, checking TDRE bit in UART0_S1. Page 729. */
297  //while((UART0_S1 & 0x80) != 0x80);
298  UART1_D = (uint8_t)outChar; /* Write char to UART0 Data buffer. Page 734. */
299 }
300 
301 void UART2_PutChar(char outChar) /* Put single character into UART2 output register */
302 {
303  while(!(UART2_S1 & UART_S1_TDRE_MASK)); /* Check for space in TX Buffer, checking TDRE bit in UART0_S1. Page 729. */
304  //while((UART0_S1 & 0x80) != 0x80);
305  UART2_D = (uint8_t)outChar; /* Write char to UART0 Data buffer. Page 734. */
306 }
307 
308 
309 
310 void UART_SendString(uint8_t uart, const unsigned char *str)
311 {
312  switch (uart){
313  case 0: UART0_SendString(str);
314  break;
315  case 1: UART1_SendString(str);
316  break;
317  case 2: UART2_SendString(str);
318  break;
319  default:
320  break;
321  }
322 
323 }
324 
325 void UART0_SendString(const unsigned char *str)
326 {
327  while(*str!='\0')
328  {
329  UART0_PutChar(*str++);
330  }
331 }
332 
333 void UART1_SendString(const unsigned char *str)
334 {
335  while(*str!='\0')
336  {
337  UART1_PutChar(*str++);
338  }
339 }
340 
341 void UART2_SendString(const unsigned char *str)
342 {
343  while(*str!='\0')
344  {
345  UART2_PutChar(*str++);
346  }
347 }
348 
349 
350 /*-----------------------------------------------------------------------------------------------------------------------------------*/
351 /* Interrupt Control Functions */
352 void UART0_IRQ_en(void)
353 {
354  UART0_C2 |= UART_C2_RIE_MASK; /* UART0_C2: enable RX interrupt, Page 728. */
355 }
356 
357 void UART1_IRQ_en(void)
358 {
359  UART1_C2 |= UART_C2_RIE_MASK; /* UART1_C2: enable RX interrupt, Page 753. */
360 }
361 
362 void UART2_IRQ_en(void)
363 {
364  UART2_C2 |= UART_C2_RIE_MASK; /* UART2_C2: enable RX interrupt, Page 753. */
365 }
366 
367 
368 void UART0_IRQ_dis(void)
369 {
370  UART0_C2 &= ~UART_C2_RIE_MASK; /* UART0_C2: enable RX interrupt, Page 728. */
371 }
372 
373 void UART1_IRQ_dis(void)
374 {
375  UART1_C2 &= ~UART_C2_RIE_MASK; /* UART1_C2: enable RX interrupt, Page 753. */
376 }
377 
378 void UART2_IRQ_dis(void)
379 {
380  UART2_C2 &= ~UART_C2_RIE_MASK; /* UART2_C2: enable RX interrupt, Page 753. */
381 }
382 
383 
384 /*-----------------------------------------------------------------------------------------------------------------------------------*/
385 /* Interrupt Handler */
386 void UART0_IRQHandler(void) /* UART0 Interrupt Handler */
387 {
388  register uint16_t UART0_IntStatReg = UART0_S1; /* Copy of UART_S1, register for speed. */
389  /* Check for error flags */
390  if (UART0_IntStatReg & (UART_S1_OR_MASK | UART_S1_NF_MASK | UART_S1_FE_MASK | UART_S1_PF_MASK))
391  {
392  UART0_S1 = (uint8_t)UART_S1_Err; /* Write to status register to acknowledge error. */
393  (void) UART0_D; /* Dummy read of input data. */
394  UART0_IntStatReg &= (uint8_t)~UART_S1_RDRF_MASK; /* Clear RDRF flag so that data is junked. */
395  }
396  if (UART0_C2 & UART_C2_TIE_MASK) /* TX Interrupt enabled */
397  {
398  UART0_C2 &= (uint8_t)~UART_C2_TIE_MASK; /* We should never get here, disable TX interrupt */
399  }
400  if (UART0_IntStatReg & UART_S1_RDRF_MASK) /* RX Interrupt */
401  {
402  register uint8_t inChar = UART0_D; /* Read input data */
403  if (UART0_callback != NULL) /* If a call back function has been registered */
404  {
405  (*UART0_callback)(inChar); /* Call it and send received character */
406  }
407  else /* else */
408  {
409  #ifdef DEBUG /* Break if in debug, otherwise do nothing. */
410  __asm("bkpt");
411  #endif
412  //UART0_PutChar(inChar); /* Echo the character back out of UART0 */
413  }
414  }
415 }
416 
417 void UART1_IRQHandler(void) /* UART1 Interrupt Handler */
418 {
419  register uint16_t UART1_IntStatReg = UART1_S1; /* Copy of UART_S1, register for speed. */
420  /* Check for error flags */
421  if (UART1_IntStatReg & (UART_S1_OR_MASK | UART_S1_NF_MASK | UART_S1_FE_MASK | UART_S1_PF_MASK))
422  {
423  (void) UART1_D; /* Dummy read of input data. */
424  UART1_IntStatReg &= (uint8_t)~UART_S1_RDRF_MASK; /* Clear RDRF flag so that data is junked. */
425  }
426  if (UART1_C2 & UART_C2_TIE_MASK) /* TX Interrupt enabled */
427  {
428  UART1_C2 &= (uint8_t)~UART_C2_TIE_MASK; /* We should never get here, disable TX interrupt */
429  }
430  if (UART1_IntStatReg & UART_S1_RDRF_MASK) /* RX Interrupt */
431  {
432  register uint8_t inChar = UART1_D; /* Read input data */
433  if (UART1_callback != NULL) /* If a call back function has been registered */
434  {
435  (*UART1_callback)(inChar); /* Call it and send received character */
436  }
437  else /* else */
438  {
439  #ifdef DEBUG /* Break if in debug, otherwise do nothing. */
440  __asm("bkpt");
441  #endif
442  }
443  }
444 }
445 
446 void UART2_IRQHandler(void) /* UART2 Interrupt Handler */
447 {
448  register uint16_t UART2_IntStatReg = UART2_S1; /* Copy of UART_S1, register for speed. */
449  /* Check for error flags */
450  if (UART2_IntStatReg & (UART_S1_OR_MASK | UART_S1_NF_MASK | UART_S1_FE_MASK | UART_S1_PF_MASK))
451  {
452  (void) UART2_D; /* Dummy read of input data. */
453  UART2_IntStatReg &= (uint8_t)~UART_S1_RDRF_MASK; /* Clear RDRF flag so that data is junked. */
454  }
455  if (UART2_C2 & UART_C2_TIE_MASK) /* TX Interrupt enabled */
456  {
457  UART2_C2 &= (uint8_t)~UART_C2_TIE_MASK; /* We should never get here, disable TX interrupt */
458  }
459  if (UART2_IntStatReg & UART_S1_RDRF_MASK) /* RX Interrupt */
460  {
461  register uint8_t inChar = UART2_D; /* Read input data */
462  if (UART2_callback != NULL) /* If a call back function has been registered */
463  {
464  (*UART2_callback)(inChar); /* Call it and send received character */
465  }
466  else /* else */
467  {
468  #ifdef DEBUG /* Break if in debug, otherwise do nothing. */
469  __asm("bkpt");
470  #endif
471  }
472  }
473 }
474 
NVIC_Set_Priority
void NVIC_Set_Priority(uint32_t IRQ, uint8_t priority)
Set the priority of the specified interrupt in the ARM NVIC.
Definition: nvic.c:142
MKL25Z4.h
CMSIS Peripheral Access Layer for MKL25Z4.
NULL
#define NULL
The null pointer.
Definition: platform-common.h:186
NVIC_ENABLE_INT
void NVIC_ENABLE_INT(uint32_t IRQ)
Enable specified interrupt in the ARM NVIC.
Definition: nvic.c:80
Generated on Thu Jul 6 2017 20:52:46 for Contiki 3.x by   doxygen 1.8.6