MKL25Z4.h File Reference

CMSIS Peripheral Access Layer for MKL25Z4. More...

#include <stdint.h>
#include "core_cm0plus.h"
#include "system_MKL25Z4.h"

Go to the source code of this file.

Data Structures
struct	ADC_Type
	ADC - Register Layout Typedef. More...
struct	CMP_Type
	CMP - Register Layout Typedef. More...
struct	DAC_Type
	DAC - Register Layout Typedef. More...
struct	DMA_Type
	DMA - Register Layout Typedef. More...
struct	DMAMUX_Type
	DMAMUX - Register Layout Typedef. More...
struct	FGPIO_Type
	FGPIO - Register Layout Typedef. More...
struct	FTFA_Type
	FTFA - Register Layout Typedef. More...
struct	GPIO_Type
	GPIO - Register Layout Typedef. More...
struct	I2C_Type
	I2C - Register Layout Typedef. More...
struct	LLWU_Type
	LLWU - Register Layout Typedef. More...
struct	LPTMR_Type
	LPTMR - Register Layout Typedef. More...
struct	MCG_Type
	MCG - Register Layout Typedef. More...
struct	MCM_Type
	MCM - Register Layout Typedef. More...
struct	MTB_Type
	MTB - Register Layout Typedef. More...
struct	MTBDWT_Type
	MTBDWT - Register Layout Typedef. More...
struct	NV_Type
	NV - Register Layout Typedef. More...
struct	OSC_Type
	OSC - Register Layout Typedef. More...
struct	PIT_Type
	PIT - Register Layout Typedef. More...
struct	PMC_Type
	PMC - Register Layout Typedef. More...
struct	PORT_Type
	PORT - Register Layout Typedef. More...
struct	RCM_Type
	RCM - Register Layout Typedef. More...
struct	ROM_Type
	ROM - Register Layout Typedef. More...
struct	RTC_Type
	RTC - Register Layout Typedef. More...
struct	SIM_Type
	SIM - Register Layout Typedef. More...
struct	SMC_Type
	SMC - Register Layout Typedef. More...
struct	SPI_Type
	SPI - Register Layout Typedef. More...
struct	TPM_Type
	TPM - Register Layout Typedef. More...
struct	TSI_Type
	TSI - Register Layout Typedef. More...
struct	UART_Type
	UART - Register Layout Typedef. More...
struct	UART0_Type
	UART0 - Register Layout Typedef. More...
struct	USB_Type
	USB - Register Layout Typedef. More...

Macros
#define	MCU_MEM_MAP_VERSION   0x0200u
	Memory map major version (memory maps with equal major version number are compatible)
#define	MCU_MEM_MAP_VERSION_MINOR   0x0005u
	Memory map minor version.
#define	NUMBER_OF_INT_VECTORS   48
	Interrupt Number Definitions. More...
#define	__CM0PLUS_REV   0x0000
	Core revision r0p0.
#define	__MPU_PRESENT   0
	Defines if an MPU is present or not.
#define	__VTOR_PRESENT   1
	Defines if an MPU is present or not.
#define	__NVIC_PRIO_BITS   2
	Number of priority bits implemented in the NVIC.
#define	__Vendor_SysTickConfig   0
	Vendor specific implementation of SysTickConfig is defined.
#define	ADC0_BASE   (0x4003B000u)
	Peripheral ADC0 base address.
#define	ADC0   ((ADC_Type *)ADC0_BASE)
	Peripheral ADC0 base pointer.
#define	ADC_BASE_ADDRS   { ADC0_BASE }
	Array initializer of ADC peripheral base addresses.
#define	ADC_BASE_PTRS   { ADC0 }
	Array initializer of ADC peripheral base pointers.
#define	ADC_IRQS   { ADC0_IRQn }
	Interrupt vectors for the ADC peripheral type.
#define	CMP0_BASE   (0x40073000u)
	Peripheral CMP0 base address.
#define	CMP0   ((CMP_Type *)CMP0_BASE)
	Peripheral CMP0 base pointer.
#define	CMP_BASE_ADDRS   { CMP0_BASE }
	Array initializer of CMP peripheral base addresses.
#define	CMP_BASE_PTRS   { CMP0 }
	Array initializer of CMP peripheral base pointers.
#define	CMP_IRQS   { CMP0_IRQn }
	Interrupt vectors for the CMP peripheral type.
#define	DAC0_BASE   (0x4003F000u)
	Peripheral DAC0 base address.
#define	DAC0   ((DAC_Type *)DAC0_BASE)
	Peripheral DAC0 base pointer.
#define	DAC_BASE_ADDRS   { DAC0_BASE }
	Array initializer of DAC peripheral base addresses.
#define	DAC_BASE_PTRS   { DAC0 }
	Array initializer of DAC peripheral base pointers.
#define	DAC_IRQS   { DAC0_IRQn }
	Interrupt vectors for the DAC peripheral type.
#define	DMA_BASE   (0x40008000u)
	Peripheral DMA base address.
#define	DMA0   ((DMA_Type *)DMA_BASE)
	Peripheral DMA base pointer.
#define	DMA_BASE_ADDRS   { DMA_BASE }
	Array initializer of DMA peripheral base addresses.
#define	DMA_BASE_PTRS   { DMA0 }
	Array initializer of DMA peripheral base pointers.
#define	DMA_CHN_IRQS   { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
	Interrupt vectors for the DMA peripheral type.
#define	DMAMUX0_BASE   (0x40021000u)
	Peripheral DMAMUX0 base address.
#define	DMAMUX0   ((DMAMUX_Type *)DMAMUX0_BASE)
	Peripheral DMAMUX0 base pointer.
#define	DMAMUX_BASE_ADDRS   { DMAMUX0_BASE }
	Array initializer of DMAMUX peripheral base addresses.
#define	DMAMUX_BASE_PTRS   { DMAMUX0 }
	Array initializer of DMAMUX peripheral base pointers.
#define	FGPIOA_BASE   (0xF80FF000u)
	Peripheral FGPIOA base address.
#define	FGPIOA   ((FGPIO_Type *)FGPIOA_BASE)
	Peripheral FGPIOA base pointer.
#define	FGPIOB_BASE   (0xF80FF040u)
	Peripheral FGPIOB base address.
#define	FGPIOB   ((FGPIO_Type *)FGPIOB_BASE)
	Peripheral FGPIOB base pointer.
#define	FGPIOC_BASE   (0xF80FF080u)
	Peripheral FGPIOC base address.
#define	FGPIOC   ((FGPIO_Type *)FGPIOC_BASE)
	Peripheral FGPIOC base pointer.
#define	FGPIOD_BASE   (0xF80FF0C0u)
	Peripheral FGPIOD base address.
#define	FGPIOD   ((FGPIO_Type *)FGPIOD_BASE)
	Peripheral FGPIOD base pointer.
#define	FGPIOE_BASE   (0xF80FF100u)
	Peripheral FGPIOE base address.
#define	FGPIOE   ((FGPIO_Type *)FGPIOE_BASE)
	Peripheral FGPIOE base pointer.
#define	FGPIO_BASE_ADDRS   { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
	Array initializer of FGPIO peripheral base addresses.
#define	FGPIO_BASE_PTRS   { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
	Array initializer of FGPIO peripheral base pointers.
#define	FTFA_BASE   (0x40020000u)
	Peripheral FTFA base address.
#define	FTFA   ((FTFA_Type *)FTFA_BASE)
	Peripheral FTFA base pointer.
#define	FTFA_BASE_ADDRS   { FTFA_BASE }
	Array initializer of FTFA peripheral base addresses.
#define	FTFA_BASE_PTRS   { FTFA }
	Array initializer of FTFA peripheral base pointers.
#define	FTFA_COMMAND_COMPLETE_IRQS   { FTFA_IRQn }
	Interrupt vectors for the FTFA peripheral type.
#define	GPIOA_BASE   (0x400FF000u)
	Peripheral GPIOA base address.
#define	GPIOA   ((GPIO_Type *)GPIOA_BASE)
	Peripheral GPIOA base pointer.
#define	GPIOB_BASE   (0x400FF040u)
	Peripheral GPIOB base address.
#define	GPIOB   ((GPIO_Type *)GPIOB_BASE)
	Peripheral GPIOB base pointer.
#define	GPIOC_BASE   (0x400FF080u)
	Peripheral GPIOC base address.
#define	GPIOC   ((GPIO_Type *)GPIOC_BASE)
	Peripheral GPIOC base pointer.
#define	GPIOD_BASE   (0x400FF0C0u)
	Peripheral GPIOD base address.
#define	GPIOD   ((GPIO_Type *)GPIOD_BASE)
	Peripheral GPIOD base pointer.
#define	GPIOE_BASE   (0x400FF100u)
	Peripheral GPIOE base address.
#define	GPIOE   ((GPIO_Type *)GPIOE_BASE)
	Peripheral GPIOE base pointer.
#define	GPIO_BASE_ADDRS   { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
	Array initializer of GPIO peripheral base addresses.
#define	GPIO_BASE_PTRS   { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
	Array initializer of GPIO peripheral base pointers.
#define	I2C0_BASE   (0x40066000u)
	Peripheral I2C0 base address.
#define	I2C0   ((I2C_Type *)I2C0_BASE)
	Peripheral I2C0 base pointer.
#define	I2C1_BASE   (0x40067000u)
	Peripheral I2C1 base address.
#define	I2C1   ((I2C_Type *)I2C1_BASE)
	Peripheral I2C1 base pointer.
#define	I2C_BASE_ADDRS   { I2C0_BASE, I2C1_BASE }
	Array initializer of I2C peripheral base addresses.
#define	I2C_BASE_PTRS   { I2C0, I2C1 }
	Array initializer of I2C peripheral base pointers.
#define	I2C_IRQS   { I2C0_IRQn, I2C1_IRQn }
	Interrupt vectors for the I2C peripheral type.
#define	LLWU_BASE   (0x4007C000u)
	Peripheral LLWU base address.
#define	LLWU   ((LLWU_Type *)LLWU_BASE)
	Peripheral LLWU base pointer.
#define	LLWU_BASE_ADDRS   { LLWU_BASE }
	Array initializer of LLWU peripheral base addresses.
#define	LLWU_BASE_PTRS   { LLWU }
	Array initializer of LLWU peripheral base pointers.
#define	LLWU_IRQS   { LLWU_IRQn }
	Interrupt vectors for the LLWU peripheral type.
#define	LPTMR0_BASE   (0x40040000u)
	Peripheral LPTMR0 base address.
#define	LPTMR0   ((LPTMR_Type *)LPTMR0_BASE)
	Peripheral LPTMR0 base pointer.
#define	LPTMR_BASE_ADDRS   { LPTMR0_BASE }
	Array initializer of LPTMR peripheral base addresses.
#define	LPTMR_BASE_PTRS   { LPTMR0 }
	Array initializer of LPTMR peripheral base pointers.
#define	LPTMR_IRQS   { LPTMR0_IRQn }
	Interrupt vectors for the LPTMR peripheral type.
#define	MCG_BASE   (0x40064000u)
	Peripheral MCG base address.
#define	MCG   ((MCG_Type *)MCG_BASE)
	Peripheral MCG base pointer.
#define	MCG_BASE_ADDRS   { MCG_BASE }
	Array initializer of MCG peripheral base addresses.
#define	MCG_BASE_PTRS   { MCG }
	Array initializer of MCG peripheral base pointers.
#define	MCG_IRQS   { MCG_IRQn }
	Interrupt vectors for the MCG peripheral type.
#define	MCM_BASE   (0xF0003000u)
	Peripheral MCM base address.
#define	MCM   ((MCM_Type *)MCM_BASE)
	Peripheral MCM base pointer.
#define	MCM_BASE_ADDRS   { MCM_BASE }
	Array initializer of MCM peripheral base addresses.
#define	MCM_BASE_PTRS   { MCM }
	Array initializer of MCM peripheral base pointers.
#define	MTB_BASE   (0xF0000000u)
	Peripheral MTB base address.
#define	MTB   ((MTB_Type *)MTB_BASE)
	Peripheral MTB base pointer.
#define	MTB_BASE_ADDRS   { MTB_BASE }
	Array initializer of MTB peripheral base addresses.
#define	MTB_BASE_PTRS   { MTB }
	Array initializer of MTB peripheral base pointers.
#define	MTBDWT_BASE   (0xF0001000u)
	Peripheral MTBDWT base address.
#define	MTBDWT   ((MTBDWT_Type *)MTBDWT_BASE)
	Peripheral MTBDWT base pointer.
#define	MTBDWT_BASE_ADDRS   { MTBDWT_BASE }
	Array initializer of MTBDWT peripheral base addresses.
#define	MTBDWT_BASE_PTRS   { MTBDWT }
	Array initializer of MTBDWT peripheral base pointers.
#define	FTFA_FlashConfig_BASE   (0x400u)
	Peripheral FTFA_FlashConfig base address.
#define	FTFA_FlashConfig   ((NV_Type *)FTFA_FlashConfig_BASE)
	Peripheral FTFA_FlashConfig base pointer.
#define	NV_BASE_ADDRS   { FTFA_FlashConfig_BASE }
	Array initializer of NV peripheral base addresses.
#define	NV_BASE_PTRS   { FTFA_FlashConfig }
	Array initializer of NV peripheral base pointers.
#define	OSC0_BASE   (0x40065000u)
	Peripheral OSC0 base address.
#define	OSC0   ((OSC_Type *)OSC0_BASE)
	Peripheral OSC0 base pointer.
#define	OSC_BASE_ADDRS   { OSC0_BASE }
	Array initializer of OSC peripheral base addresses.
#define	OSC_BASE_PTRS   { OSC0 }
	Array initializer of OSC peripheral base pointers.
#define	PIT_BASE   (0x40037000u)
	Peripheral PIT base address.
#define	PIT   ((PIT_Type *)PIT_BASE)
	Peripheral PIT base pointer.
#define	PIT_BASE_ADDRS   { PIT_BASE }
	Array initializer of PIT peripheral base addresses.
#define	PIT_BASE_PTRS   { PIT }
	Array initializer of PIT peripheral base pointers.
#define	PIT_IRQS   { PIT_IRQn, PIT_IRQn }
	Interrupt vectors for the PIT peripheral type.
#define	PMC_BASE   (0x4007D000u)
	Peripheral PMC base address.
#define	PMC   ((PMC_Type *)PMC_BASE)
	Peripheral PMC base pointer.
#define	PMC_BASE_ADDRS   { PMC_BASE }
	Array initializer of PMC peripheral base addresses.
#define	PMC_BASE_PTRS   { PMC }
	Array initializer of PMC peripheral base pointers.
#define	PMC_IRQS   { LVD_LVW_IRQn }
	Interrupt vectors for the PMC peripheral type.
#define	PORTA_BASE   (0x40049000u)
	Peripheral PORTA base address.
#define	PORTA   ((PORT_Type *)PORTA_BASE)
	Peripheral PORTA base pointer.
#define	PORTB_BASE   (0x4004A000u)
	Peripheral PORTB base address.
#define	PORTB   ((PORT_Type *)PORTB_BASE)
	Peripheral PORTB base pointer.
#define	PORTC_BASE   (0x4004B000u)
	Peripheral PORTC base address.
#define	PORTC   ((PORT_Type *)PORTC_BASE)
	Peripheral PORTC base pointer.
#define	PORTD_BASE   (0x4004C000u)
	Peripheral PORTD base address.
#define	PORTD   ((PORT_Type *)PORTD_BASE)
	Peripheral PORTD base pointer.
#define	PORTE_BASE   (0x4004D000u)
	Peripheral PORTE base address.
#define	PORTE   ((PORT_Type *)PORTE_BASE)
	Peripheral PORTE base pointer.
#define	PORT_BASE_ADDRS   { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
	Array initializer of PORT peripheral base addresses.
#define	PORT_BASE_PTRS   { PORTA, PORTB, PORTC, PORTD, PORTE }
	Array initializer of PORT peripheral base pointers.
#define	PORT_IRQS   { PORTA_IRQn, NotAvail_IRQn, NotAvail_IRQn, PORTD_IRQn, NotAvail_IRQn }
	Interrupt vectors for the PORT peripheral type.
#define	RCM_BASE   (0x4007F000u)
	Peripheral RCM base address.
#define	RCM   ((RCM_Type *)RCM_BASE)
	Peripheral RCM base pointer.
#define	RCM_BASE_ADDRS   { RCM_BASE }
	Array initializer of RCM peripheral base addresses.
#define	RCM_BASE_PTRS   { RCM }
	Array initializer of RCM peripheral base pointers.
#define	ROM_BASE   (0xF0002000u)
	Peripheral ROM base address.
#define	ROM   ((ROM_Type *)ROM_BASE)
	Peripheral ROM base pointer.
#define	ROM_BASE_ADDRS   { ROM_BASE }
	Array initializer of ROM peripheral base addresses.
#define	ROM_BASE_PTRS   { ROM }
	Array initializer of ROM peripheral base pointers.
#define	RTC_BASE   (0x4003D000u)
	Peripheral RTC base address.
#define	RTC   ((RTC_Type *)RTC_BASE)
	Peripheral RTC base pointer.
#define	RTC_BASE_ADDRS   { RTC_BASE }
	Array initializer of RTC peripheral base addresses.
#define	RTC_BASE_PTRS   { RTC }
	Array initializer of RTC peripheral base pointers.
#define	RTC_IRQS   { RTC_IRQn }
	Interrupt vectors for the RTC peripheral type.
#define	SIM_BASE   (0x40047000u)
	Peripheral SIM base address.
#define	SIM   ((SIM_Type *)SIM_BASE)
	Peripheral SIM base pointer.
#define	SIM_BASE_ADDRS   { SIM_BASE }
	Array initializer of SIM peripheral base addresses.
#define	SIM_BASE_PTRS   { SIM }
	Array initializer of SIM peripheral base pointers.
#define	SMC_BASE   (0x4007E000u)
	Peripheral SMC base address.
#define	SMC   ((SMC_Type *)SMC_BASE)
	Peripheral SMC base pointer.
#define	SMC_BASE_ADDRS   { SMC_BASE }
	Array initializer of SMC peripheral base addresses.
#define	SMC_BASE_PTRS   { SMC }
	Array initializer of SMC peripheral base pointers.
#define	SPI0_BASE   (0x40076000u)
	Peripheral SPI0 base address.
#define	SPI0   ((SPI_Type *)SPI0_BASE)
	Peripheral SPI0 base pointer.
#define	SPI1_BASE   (0x40077000u)
	Peripheral SPI1 base address.
#define	SPI1   ((SPI_Type *)SPI1_BASE)
	Peripheral SPI1 base pointer.
#define	SPI_BASE_ADDRS   { SPI0_BASE, SPI1_BASE }
	Array initializer of SPI peripheral base addresses.
#define	SPI_BASE_PTRS   { SPI0, SPI1 }
	Array initializer of SPI peripheral base pointers.
#define	SPI_IRQS   { SPI0_IRQn, SPI1_IRQn }
	Interrupt vectors for the SPI peripheral type.
#define	TPM0_BASE   (0x40038000u)
	Peripheral TPM0 base address.
#define	TPM0   ((TPM_Type *)TPM0_BASE)
	Peripheral TPM0 base pointer.
#define	TPM1_BASE   (0x40039000u)
	Peripheral TPM1 base address.
#define	TPM1   ((TPM_Type *)TPM1_BASE)
	Peripheral TPM1 base pointer.
#define	TPM2_BASE   (0x4003A000u)
	Peripheral TPM2 base address.
#define	TPM2   ((TPM_Type *)TPM2_BASE)
	Peripheral TPM2 base pointer.
#define	TPM_BASE_ADDRS   { TPM0_BASE, TPM1_BASE, TPM2_BASE }
	Array initializer of TPM peripheral base addresses.
#define	TPM_BASE_PTRS   { TPM0, TPM1, TPM2 }
	Array initializer of TPM peripheral base pointers.
#define	TPM_IRQS   { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
	Interrupt vectors for the TPM peripheral type.
#define	TSI0_BASE   (0x40045000u)
	Peripheral TSI0 base address.
#define	TSI0   ((TSI_Type *)TSI0_BASE)
	Peripheral TSI0 base pointer.
#define	TSI_BASE_ADDRS   { TSI0_BASE }
	Array initializer of TSI peripheral base addresses.
#define	TSI_BASE_PTRS   { TSI0 }
	Array initializer of TSI peripheral base pointers.
#define	TSI_IRQS   { TSI0_IRQn }
	Interrupt vectors for the TSI peripheral type.
#define	UART1_BASE   (0x4006B000u)
	Peripheral UART1 base address.
#define	UART1   ((UART_Type *)UART1_BASE)
	Peripheral UART1 base pointer.
#define	UART2_BASE   (0x4006C000u)
	Peripheral UART2 base address.
#define	UART2   ((UART_Type *)UART2_BASE)
	Peripheral UART2 base pointer.
#define	UART_BASE_ADDRS   { 0u, UART1_BASE, UART2_BASE }
	Array initializer of UART peripheral base addresses.
#define	UART_BASE_PTRS   { (UART_Type *)0u, UART1, UART2 }
	Array initializer of UART peripheral base pointers.
#define	UART_RX_TX_IRQS   { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
	Interrupt vectors for the UART peripheral type.
#define	UART0_BASE   (0x4006A000u)
	Peripheral UART0 base address.
#define	UART0   ((UART0_Type *)UART0_BASE)
	Peripheral UART0 base pointer.
#define	UART0_BASE_ADDRS   { UART0_BASE }
	Array initializer of UART0 peripheral base addresses.
#define	UART0_BASE_PTRS   { UART0 }
	Array initializer of UART0 peripheral base pointers.
#define	UART0_RX_TX_IRQS   { UART0_IRQn }
	Interrupt vectors for the UART0 peripheral type.
#define	USB0_BASE   (0x40072000u)
	Peripheral USB0 base address.
#define	USB0   ((USB_Type *)USB0_BASE)
	Peripheral USB0 base pointer.
#define	USB_BASE_ADDRS   { USB0_BASE }
	Array initializer of USB peripheral base addresses.
#define	USB_BASE_PTRS   { USB0 }
	Array initializer of USB peripheral base pointers.
#define	USB_IRQS   { USB0_IRQn }
	Interrupt vectors for the USB peripheral type.

Enumerations
enum	IRQn {   NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5,   PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_IRQn = 0, DMA1_IRQn = 1,   DMA2_IRQn = 2, DMA3_IRQn = 3, Reserved20_IRQn = 4, FTFA_IRQn = 5,   LVD_LVW_IRQn = 6, LLWU_IRQn = 7, I2C0_IRQn = 8, I2C1_IRQn = 9,   SPI0_IRQn = 10, SPI1_IRQn = 11, UART0_IRQn = 12, UART1_IRQn = 13,   UART2_IRQn = 14, ADC0_IRQn = 15, CMP0_IRQn = 16, TPM0_IRQn = 17,   TPM1_IRQn = 18, TPM2_IRQn = 19, RTC_IRQn = 20, RTC_Seconds_IRQn = 21,   PIT_IRQn = 22, Reserved39_IRQn = 23, USB0_IRQn = 24, DAC0_IRQn = 25,   TSI0_IRQn = 26, MCG_IRQn = 27, LPTMR0_IRQn = 28, Reserved45_IRQn = 29,   PORTA_IRQn = 30, PORTD_IRQn = 31 }

Detailed Description

CMSIS Peripheral Access Layer for MKL25Z4.

Version

2.5

Date

2015-02-19 CMSIS Peripheral Access Layer for MKL25Z4

Definition in file MKL25Z4.h.