60 #include "contiki-conf.h"
80 #define ATMEGA128RFA1 6
81 #define ATMEGA256RFR2 7
83 #if PLATFORM_TYPE == RCB_B
88 # define MOSIPIN (0x02)
89 # define MISOPIN (0x03)
90 # define SCKPIN (0x01)
92 # define RSTPIN (0x05)
94 # define IRQPIN (0x04)
96 # define SLPTRPIN (0x04)
98 #elif PLATFORM_TYPE == ZIGBIT
101 # define SSPIN (0x00)
103 # define MOSIPIN (0x02)
104 # define MISOPIN (0x03)
105 # define SCKPIN (0x01)
107 # define RSTPIN (0x07)
109 # define IRQPIN (0x05)
111 # define SLPTRPIN (0x04)
114 #elif PLATFORM_TYPE == RAVEN_D
117 # define SSPIN (0x04)
119 # define MOSIPIN (0x05)
120 # define MISOPIN (0x06)
121 # define SCKPIN (0x07)
123 # define RSTPIN (0x01)
125 # define IRQPIN (0x06)
127 # define SLPTRPIN (0x03)
129 #elif PLATFORM_TYPE == RAVENUSB_C
132 # define SSPIN (0x00)
134 # define MOSIPIN (0x02)
135 # define MISOPIN (0x03)
136 # define SCKPIN (0x01)
138 # define RSTPIN (0x05)
140 # define IRQPIN (0x04)
142 # define SLPTRPIN (0x04)
144 #elif PLATFORM_TYPE == ATMEGA128RFA1
146 # define SLPTRPORT TRXPR
149 #elif PLATFORM_TYPE == ATMEGA256RFR2
151 # define SLPTRPORT TRXPR
154 #elif CONTIKI_TARGET_MULLE
171 #elif PLATFORM_TYPE == IRIS
174 # define SSPIN (0x00)
176 # define MOSIPIN (0x02)
177 # define MISOPIN (0x03)
178 # define SCKPIN (0x01)
180 # define RSTPIN (0x06)
182 # define IRQPIN (0x04)
184 # define SLPTRPIN (0x07)
187 #error "PLATFORM_TYPE undefined in hal.h"
193 #define SSPORT SPIPORT
197 #define SCKPORT SPIPORT
201 #define MOSIPORT SPIPORT
205 #define MISOPORT SPIPORT
220 #define CAT(x, y) x##y
221 #define DDR(x) CAT(DDR, x)
222 #define PORT(x) CAT(PORT, x)
223 #define PIN(x) CAT(PIN, x)
227 #if defined(CONTIKI_TARGET_MULLE)
228 #define CAT(x, y) x##y.BYTE
229 #define DDR(x) CAT(PD, x)
230 #define PORT(x) CAT(P, x)
231 #define PIN(x) CAT(P, x)
242 #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
244 #define hal_set_rst_low( ) ( TRXPR &= ~( 1 << TRXRST ) )
245 #define hal_set_rst_high( ) ( TRXPR |= ( 1 << TRXRST ) )
246 #define hal_set_slptr_high( ) ( TRXPR |= ( 1 << SLPTR ) )
247 #define hal_set_slptr_low( ) ( TRXPR &= ~( 1 << SLPTR ) )
248 #define hal_get_slptr( ) ( TRXPR & ( 1 << SLPTR ) )
251 #define SLP_TR SLPTRPIN
252 #define DDR_SLP_TR DDR( SLPTRPORT )
253 #define PORT_SLP_TR PORT( SLPTRPORT )
254 #define PIN_SLP_TR PIN( SLPTRPORT )
255 #define hal_set_slptr_high( ) ( PORT_SLP_TR |= ( 1 << SLP_TR ) )
256 #define hal_set_slptr_low( ) ( PORT_SLP_TR &= ~( 1 << SLP_TR ) )
257 #define hal_get_slptr( ) ( PIN_SLP_TR & ( 1 << SLP_TR ) )
259 #define DDR_RST DDR( RSTPORT )
260 #define PORT_RST PORT( RSTPORT )
261 #define PIN_RST PIN( RSTPORT )
262 #define hal_set_rst_high( ) ( PORT_RST |= ( 1 << RST ) )
263 #define hal_set_rst_low( ) ( PORT_RST &= ~( 1 << RST ) )
264 #define hal_get_rst( ) ( ( PIN_RST & ( 1 << RST ) ) >> RST )
265 #define HAL_SS_PIN SSPIN
266 #define HAL_SCK_PIN SCKPIN
267 #define HAL_MOSI_PIN MOSIPIN
268 #define HAL_MISO_PIN MISOPIN
269 #define HAL_PORT_SPI PORT( SPIPORT )
270 #define HAL_PORT_SS PORT( SSPORT )
271 #define HAL_PORT_SCK PORT( SCKPORT )
272 #define HAL_PORT_MOSI PORT( MOSIPORT )
273 #define HAL_PORT_MISO PORT( MISOPORT )
274 #define HAL_DDR_SPI DDR( SPIPORT )
275 #define HAL_DDR_SS DDR( SSPORT )
276 #define HAL_DDR_SCK DDR( SCKPORT )
277 #define HAL_DDR_MOSI DDR( MOSIPORT )
278 #define HAL_DDR_MISO DDR( MISOPORT )
279 #define HAL_DD_SS SSPIN
280 #define HAL_DD_SCK SCKPIN
281 #define HAL_DD_MOSI MOSIPIN
282 #define HAL_DD_MISO MISOPIN
288 #define HAL_SS_HIGH( ) (HAL_PORT_SS |= ( 1 << HAL_SS_PIN ))
289 #define HAL_SS_LOW( ) (HAL_PORT_SS &= ~( 1 << HAL_SS_PIN ))
293 #if PLATFORM_TYPE == ZIGBIT
295 #define RADIO_VECT INT5_vect
296 #define HAL_ENABLE_RADIO_INTERRUPT( ) { ( EIMSK |= ( 1 << INT5 ) ) ; EICRB |= 0x0C ; PORTE &= ~(1<<PE5); DDRE &= ~(1<<DDE5); }
297 #define HAL_DISABLE_RADIO_INTERRUPT( ) ( EIMSK &= ~( 1 << INT5 ) )
299 #define RADIO_VECT TIMER1_CAPT_vect
301 #define HAL_ENABLE_RADIO_INTERRUPT( ) { TCCR1B = ( 1 << ICES1 ) | ( 1 << CS10 ); TIFR1 |= (1 << ICF1); TIMSK1 |= ( 1 << ICIE1 ) ; }
302 #define HAL_DISABLE_RADIO_INTERRUPT( ) ( TIMSK1 &= ~( 1 << ICIE1 ) )
305 #define HAL_ENABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 |= ( 1 << TOIE1 ) )
306 #define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 &= ~( 1 << TOIE1 ) )
309 #define HAL_ENTER_CRITICAL_REGION( ) {uint8_t volatile saved_sreg = SREG; cli( )
313 #define HAL_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;}
317 #define HAL_ENABLE_RADIO_INTERRUPT( ) ( INT1IC.BYTE |= 1 )
318 #define HAL_DISABLE_RADIO_INTERRUPT( ) ( INT1IC.BYTE &= ~(1) )
320 #define HAL_ENABLE_OVERFLOW_INTERRUPT( ) ( TB4IC.BYTE = 1 )
321 #define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TB4IC.BYTE = 0 )
324 #define HAL_ENTER_CRITICAL_REGION( ) MULLE_ENTER_CRITICAL_REGION( )
328 #define HAL_LEAVE_CRITICAL_REGION( ) MULLE_LEAVE_CRITICAL_REGION( )
335 #define hal_enable_trx_interrupt( ) HAL_ENABLE_RADIO_INTERRUPT( )
341 #define hal_disable_trx_interrupt( ) HAL_DISABLE_RADIO_INTERRUPT( )
348 #define HAL_BAT_LOW_MASK ( 0x80 )
349 #define HAL_TRX_UR_MASK ( 0x40 )
350 #define HAL_TRX_END_MASK ( 0x08 )
351 #define HAL_RX_START_MASK ( 0x04 )
352 #define HAL_PLL_UNLOCK_MASK ( 0x02 )
353 #define HAL_PLL_LOCK_MASK ( 0x01 )
355 #define HAL_MIN_FRAME_LENGTH ( 0x03 )
356 #define HAL_MAX_FRAME_LENGTH ( 0x7F )
376 #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
378 #define hal_register_read(address) address
384 #define hal_register_write(address, value) address=value
400 void hal_sram_read( uint8_t address, uint8_t length, uint8_t *data );
401 void hal_sram_write( uint8_t address, uint8_t length, uint8_t *data );
403 #ifndef RF230_CONF_RX_BUFFERS
404 #define RF230_CONF_RX_BUFFERS 1
void hal_init(void)
This function initializes the Hardware Abstraction Layer.
void hal_register_write(uint8_t address, uint8_t value)
This function writes a new value to one of the radio transceiver's registers.
uint8_t hal_subregister_read(uint8_t address, uint8_t mask, uint8_t position)
This function reads the value of a specific subregister.
void hal_subregister_write(uint8_t address, uint8_t mask, uint8_t position, uint8_t value)
This function writes a new value to one of the radio transceiver's subregisters.
#define HAL_MAX_FRAME_LENGTH
A frame should no more than 127 bytes.
uint8_t hal_register_read(uint8_t address)
This function reads data from one of the radio transceiver's registers.
void hal_frame_read(hal_rx_frame_t *rx_frame)
Transfer a frame from the radio transceiver to a RAM buffer.
void hal_sram_write(uint8_t address, uint8_t length, uint8_t *data)
Write SRAM.
void hal_frame_write(uint8_t *write_buffer, uint8_t length)
This function will download a frame to the radio transceiver's frame buffer.
void hal_sram_read(uint8_t address, uint8_t length, uint8_t *data)
Read SRAM.
This struct defines the rx data container.