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Contiki 3.x
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LLWU - Register Layout Typedef. More...
#include <cpu/arm/mkl25z/MKL25Z4.h>
Data Fields | |
| __IO uint8_t | PE1 |
| LLWU Pin Enable 1 register, offset: 0x0. | |
| __IO uint8_t | PE2 |
| LLWU Pin Enable 2 register, offset: 0x1. | |
| __IO uint8_t | PE3 |
| LLWU Pin Enable 3 register, offset: 0x2. | |
| __IO uint8_t | PE4 |
| LLWU Pin Enable 4 register, offset: 0x3. | |
| __IO uint8_t | ME |
| LLWU Module Enable register, offset: 0x4. | |
| __IO uint8_t | F1 |
| LLWU Flag 1 register, offset: 0x5. | |
| __IO uint8_t | F2 |
| LLWU Flag 2 register, offset: 0x6. | |
| __I uint8_t | F3 |
| LLWU Flag 3 register, offset: 0x7. | |
| __IO uint8_t | FILT1 |
| LLWU Pin Filter 1 register, offset: 0x8. | |
| __IO uint8_t | FILT2 |
| LLWU Pin Filter 2 register, offset: 0x9. | |
1.8.6