Contiki 3.x
MKL25Z4.h
Go to the documentation of this file.
1 /*
2 ** ###################################################################
3 ** Processors: MKL25Z128FM4
4 ** MKL25Z128FT4
5 ** MKL25Z128LH4
6 ** MKL25Z128VLK4
7 **
8 ** Compilers: Keil ARM C/C++ Compiler
9 ** Freescale C/C++ for Embedded ARM
10 ** GNU C Compiler
11 ** GNU C Compiler - CodeSourcery Sourcery G++
12 ** IAR ANSI C/C++ Compiler for ARM
13 **
14 ** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
15 ** Version: rev. 2.5, 2015-02-19
16 ** Build: b150721
17 **
18 ** Abstract:
19 ** CMSIS Peripheral Access Layer for MKL25Z4
20 **
21 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
22 ** All rights reserved.
23 **
24 ** Redistribution and use in source and binary forms, with or without modification,
25 ** are permitted provided that the following conditions are met:
26 **
27 ** o Redistributions of source code must retain the above copyright notice, this list
28 ** of conditions and the following disclaimer.
29 **
30 ** o Redistributions in binary form must reproduce the above copyright notice, this
31 ** list of conditions and the following disclaimer in the documentation and/or
32 ** other materials provided with the distribution.
33 **
34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
35 ** contributors may be used to endorse or promote products derived from this
36 ** software without specific prior written permission.
37 **
38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 **
49 ** http: www.freescale.com
50 ** mail: support@freescale.com
51 **
52 ** Revisions:
53 ** - rev. 1.0 (2012-06-13)
54 ** Initial version.
55 ** - rev. 1.1 (2012-06-21)
56 ** Update according to reference manual rev. 1.
57 ** - rev. 1.2 (2012-08-01)
58 ** Device type UARTLP changed to UART0.
59 ** - rev. 1.3 (2012-10-04)
60 ** Update according to reference manual rev. 3.
61 ** - rev. 1.4 (2012-11-22)
62 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
63 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
64 ** - rev. 1.5 (2013-04-05)
65 ** Changed start of doxygen comment.
66 ** - rev. 2.0 (2013-10-29)
67 ** Register accessor macros added to the memory map.
68 ** Symbols for Processor Expert memory map compatibility added to the memory map.
69 ** Startup file for gcc has been updated according to CMSIS 3.2.
70 ** System initialization updated.
71 ** - rev. 2.1 (2014-07-16)
72 ** Module access macro module_BASES replaced by module_BASE_PTRS.
73 ** System initialization and startup updated.
74 ** - rev. 2.2 (2014-08-22)
75 ** System initialization updated - default clock config changed.
76 ** - rev. 2.3 (2014-08-28)
77 ** Update of startup files - possibility to override DefaultISR added.
78 ** - rev. 2.4 (2014-10-14)
79 ** Interrupt INT_LPTimer renamed to INT_LPTMR0.
80 ** - rev. 2.5 (2015-02-19)
81 ** Renamed interrupt vector LLW to LLWU.
82 **
83 ** ###################################################################
84 */
85 
86 /*!
87  * @file MKL25Z4.h
88  * @version 2.5
89  * @date 2015-02-19
90  * @brief CMSIS Peripheral Access Layer for MKL25Z4
91  *
92  * CMSIS Peripheral Access Layer for MKL25Z4
93  */
94 
95 
96 /* ----------------------------------------------------------------------------
97  -- MCU activation
98  ---------------------------------------------------------------------------- */
99 
100 /* Prevention from multiple including the same memory map */
101 #if !defined(MKL25Z4_H_) /* Check if memory map has not been already included */
102 #define MKL25Z4_H_
103 #define MCU_MKL25Z4
104 
105 /* Check if another memory map has not been also included */
106 #if (defined(MCU_ACTIVE))
107  #error MKL25Z4 memory map: There is already included another memory map. Only one memory map can be included.
108 #endif /* (defined(MCU_ACTIVE)) */
109 #define MCU_ACTIVE
110 
111 #include <stdint.h>
112 
113 /** Memory map major version (memory maps with equal major version number are
114  * compatible) */
115 #define MCU_MEM_MAP_VERSION 0x0200u
116 /** Memory map minor version */
117 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
118 
119 
120 /* ----------------------------------------------------------------------------
121  -- Interrupt vector numbers
122  ---------------------------------------------------------------------------- */
123 
124 /*!
125  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
126  * @{
127  */
128 
129 /** Interrupt Number Definitions */
130 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
131 
132 typedef enum IRQn {
133  /* Auxiliary constants */
134  NotAvail_IRQn = -128, /**< Not available device specific interrupt */
135 
136  /* Core interrupts */
137  NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
138  HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
139  SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
140  PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
141  SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
142 
143  /* Device specific interrupts */
144  DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
145  DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
146  DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
147  DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
148  Reserved20_IRQn = 4, /**< Reserved interrupt */
149  FTFA_IRQn = 5, /**< Command complete and read collision */
150  LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
151  LLWU_IRQn = 7, /**< Low leakage wakeup Unit */
152  I2C0_IRQn = 8, /**< I2C0 interrupt */
153  I2C1_IRQn = 9, /**< I2C1 interrupt */
154  SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
155  SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
156  UART0_IRQn = 12, /**< UART0 status and error */
157  UART1_IRQn = 13, /**< UART1 status and error */
158  UART2_IRQn = 14, /**< UART2 status and error */
159  ADC0_IRQn = 15, /**< ADC0 interrupt */
160  CMP0_IRQn = 16, /**< CMP0 interrupt */
161  TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
162  TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
163  TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
164  RTC_IRQn = 20, /**< RTC alarm */
165  RTC_Seconds_IRQn = 21, /**< RTC seconds */
166  PIT_IRQn = 22, /**< PIT interrupt */
167  Reserved39_IRQn = 23, /**< Reserved interrupt */
168  USB0_IRQn = 24, /**< USB0 interrupt */
169  DAC0_IRQn = 25, /**< DAC0 interrupt */
170  TSI0_IRQn = 26, /**< TSI0 interrupt */
171  MCG_IRQn = 27, /**< MCG interrupt */
172  LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
173  Reserved45_IRQn = 29, /**< Reserved interrupt */
174  PORTA_IRQn = 30, /**< PORTA Pin detect */
175  PORTD_IRQn = 31 /**< PORTD Pin detect */
176 } IRQn_Type;
177 
178 /*!
179  * @}
180  */ /* end of group Interrupt_vector_numbers */
181 
182 
183 /* ----------------------------------------------------------------------------
184  -- Cortex M0 Core Configuration
185  ---------------------------------------------------------------------------- */
186 
187 /*!
188  * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
189  * @{
190  */
191 
192 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
193 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
194 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
195 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
196 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
197 
198 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
199 #include "system_MKL25Z4.h" /* Device specific configuration file */
200 
201 /*!
202  * @}
203  */ /* end of group Cortex_Core_Configuration */
204 
205 
206 /* ----------------------------------------------------------------------------
207  -- Device Peripheral Access Layer
208  ---------------------------------------------------------------------------- */
209 
210 /*!
211  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
212  * @{
213  */
214 
215 
216 /*
217 ** Start of section using anonymous unions
218 */
219 
220 #if defined(__ARMCC_VERSION)
221  #pragma push
222  #pragma anon_unions
223 #elif defined(__CWCC__)
224  #pragma push
225  #pragma cpp_extensions on
226 #elif defined(__GNUC__)
227  /* anonymous unions are enabled by default */
228 #elif defined(__IAR_SYSTEMS_ICC__)
229  #pragma language=extended
230 #else
231  #error Not supported compiler type
232 #endif
233 
234 /* ----------------------------------------------------------------------------
235  -- ADC Peripheral Access Layer
236  ---------------------------------------------------------------------------- */
237 
238 /*!
239  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
240  * @{
241  */
242 
243 /** ADC - Register Layout Typedef */
244 typedef struct {
245  __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
246  __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
247  __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
248  __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
249  __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
250  __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
251  __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
252  __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
253  __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
254  __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
255  __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
256  __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
257  __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
258  __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
259  __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
260  __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
261  __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
262  __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
263  uint8_t RESERVED_0[4];
264  __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
265  __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
266  __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
267  __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
268  __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
269  __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
270  __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
271 } ADC_Type, *ADC_MemMapPtr;
272 
273 /* ----------------------------------------------------------------------------
274  -- ADC - Register accessor macros
275  ---------------------------------------------------------------------------- */
276 
277 /*!
278  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
279  * @{
280  */
281 
282 
283 /* ADC - Register accessors */
284 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
285 #define ADC_SC1_COUNT 2
286 #define ADC_CFG1_REG(base) ((base)->CFG1)
287 #define ADC_CFG2_REG(base) ((base)->CFG2)
288 #define ADC_R_REG(base,index) ((base)->R[index])
289 #define ADC_R_COUNT 2
290 #define ADC_CV1_REG(base) ((base)->CV1)
291 #define ADC_CV2_REG(base) ((base)->CV2)
292 #define ADC_SC2_REG(base) ((base)->SC2)
293 #define ADC_SC3_REG(base) ((base)->SC3)
294 #define ADC_OFS_REG(base) ((base)->OFS)
295 #define ADC_PG_REG(base) ((base)->PG)
296 #define ADC_MG_REG(base) ((base)->MG)
297 #define ADC_CLPD_REG(base) ((base)->CLPD)
298 #define ADC_CLPS_REG(base) ((base)->CLPS)
299 #define ADC_CLP4_REG(base) ((base)->CLP4)
300 #define ADC_CLP3_REG(base) ((base)->CLP3)
301 #define ADC_CLP2_REG(base) ((base)->CLP2)
302 #define ADC_CLP1_REG(base) ((base)->CLP1)
303 #define ADC_CLP0_REG(base) ((base)->CLP0)
304 #define ADC_CLMD_REG(base) ((base)->CLMD)
305 #define ADC_CLMS_REG(base) ((base)->CLMS)
306 #define ADC_CLM4_REG(base) ((base)->CLM4)
307 #define ADC_CLM3_REG(base) ((base)->CLM3)
308 #define ADC_CLM2_REG(base) ((base)->CLM2)
309 #define ADC_CLM1_REG(base) ((base)->CLM1)
310 #define ADC_CLM0_REG(base) ((base)->CLM0)
311 
312 /*!
313  * @}
314  */ /* end of group ADC_Register_Accessor_Macros */
315 
316 
317 /* ----------------------------------------------------------------------------
318  -- ADC Register Masks
319  ---------------------------------------------------------------------------- */
320 
321 /*!
322  * @addtogroup ADC_Register_Masks ADC Register Masks
323  * @{
324  */
325 
326 /* SC1 Bit Fields */
327 #define ADC_SC1_ADCH_MASK 0x1Fu
328 #define ADC_SC1_ADCH_SHIFT 0
329 #define ADC_SC1_ADCH_WIDTH 5
330 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
331 #define ADC_SC1_DIFF_MASK 0x20u
332 #define ADC_SC1_DIFF_SHIFT 5
333 #define ADC_SC1_DIFF_WIDTH 1
334 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
335 #define ADC_SC1_AIEN_MASK 0x40u
336 #define ADC_SC1_AIEN_SHIFT 6
337 #define ADC_SC1_AIEN_WIDTH 1
338 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
339 #define ADC_SC1_COCO_MASK 0x80u
340 #define ADC_SC1_COCO_SHIFT 7
341 #define ADC_SC1_COCO_WIDTH 1
342 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
343 /* CFG1 Bit Fields */
344 #define ADC_CFG1_ADICLK_MASK 0x3u
345 #define ADC_CFG1_ADICLK_SHIFT 0
346 #define ADC_CFG1_ADICLK_WIDTH 2
347 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
348 #define ADC_CFG1_MODE_MASK 0xCu
349 #define ADC_CFG1_MODE_SHIFT 2
350 #define ADC_CFG1_MODE_WIDTH 2
351 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
352 #define ADC_CFG1_ADLSMP_MASK 0x10u
353 #define ADC_CFG1_ADLSMP_SHIFT 4
354 #define ADC_CFG1_ADLSMP_WIDTH 1
355 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
356 #define ADC_CFG1_ADIV_MASK 0x60u
357 #define ADC_CFG1_ADIV_SHIFT 5
358 #define ADC_CFG1_ADIV_WIDTH 2
359 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
360 #define ADC_CFG1_ADLPC_MASK 0x80u
361 #define ADC_CFG1_ADLPC_SHIFT 7
362 #define ADC_CFG1_ADLPC_WIDTH 1
363 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
364 /* CFG2 Bit Fields */
365 #define ADC_CFG2_ADLSTS_MASK 0x3u
366 #define ADC_CFG2_ADLSTS_SHIFT 0
367 #define ADC_CFG2_ADLSTS_WIDTH 2
368 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
369 #define ADC_CFG2_ADHSC_MASK 0x4u
370 #define ADC_CFG2_ADHSC_SHIFT 2
371 #define ADC_CFG2_ADHSC_WIDTH 1
372 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
373 #define ADC_CFG2_ADACKEN_MASK 0x8u
374 #define ADC_CFG2_ADACKEN_SHIFT 3
375 #define ADC_CFG2_ADACKEN_WIDTH 1
376 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
377 #define ADC_CFG2_MUXSEL_MASK 0x10u
378 #define ADC_CFG2_MUXSEL_SHIFT 4
379 #define ADC_CFG2_MUXSEL_WIDTH 1
380 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
381 /* R Bit Fields */
382 #define ADC_R_D_MASK 0xFFFFu
383 #define ADC_R_D_SHIFT 0
384 #define ADC_R_D_WIDTH 16
385 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
386 /* CV1 Bit Fields */
387 #define ADC_CV1_CV_MASK 0xFFFFu
388 #define ADC_CV1_CV_SHIFT 0
389 #define ADC_CV1_CV_WIDTH 16
390 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
391 /* CV2 Bit Fields */
392 #define ADC_CV2_CV_MASK 0xFFFFu
393 #define ADC_CV2_CV_SHIFT 0
394 #define ADC_CV2_CV_WIDTH 16
395 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
396 /* SC2 Bit Fields */
397 #define ADC_SC2_REFSEL_MASK 0x3u
398 #define ADC_SC2_REFSEL_SHIFT 0
399 #define ADC_SC2_REFSEL_WIDTH 2
400 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
401 #define ADC_SC2_DMAEN_MASK 0x4u
402 #define ADC_SC2_DMAEN_SHIFT 2
403 #define ADC_SC2_DMAEN_WIDTH 1
404 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
405 #define ADC_SC2_ACREN_MASK 0x8u
406 #define ADC_SC2_ACREN_SHIFT 3
407 #define ADC_SC2_ACREN_WIDTH 1
408 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
409 #define ADC_SC2_ACFGT_MASK 0x10u
410 #define ADC_SC2_ACFGT_SHIFT 4
411 #define ADC_SC2_ACFGT_WIDTH 1
412 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
413 #define ADC_SC2_ACFE_MASK 0x20u
414 #define ADC_SC2_ACFE_SHIFT 5
415 #define ADC_SC2_ACFE_WIDTH 1
416 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
417 #define ADC_SC2_ADTRG_MASK 0x40u
418 #define ADC_SC2_ADTRG_SHIFT 6
419 #define ADC_SC2_ADTRG_WIDTH 1
420 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
421 #define ADC_SC2_ADACT_MASK 0x80u
422 #define ADC_SC2_ADACT_SHIFT 7
423 #define ADC_SC2_ADACT_WIDTH 1
424 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
425 /* SC3 Bit Fields */
426 #define ADC_SC3_AVGS_MASK 0x3u
427 #define ADC_SC3_AVGS_SHIFT 0
428 #define ADC_SC3_AVGS_WIDTH 2
429 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
430 #define ADC_SC3_AVGE_MASK 0x4u
431 #define ADC_SC3_AVGE_SHIFT 2
432 #define ADC_SC3_AVGE_WIDTH 1
433 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
434 #define ADC_SC3_ADCO_MASK 0x8u
435 #define ADC_SC3_ADCO_SHIFT 3
436 #define ADC_SC3_ADCO_WIDTH 1
437 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
438 #define ADC_SC3_CALF_MASK 0x40u
439 #define ADC_SC3_CALF_SHIFT 6
440 #define ADC_SC3_CALF_WIDTH 1
441 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
442 #define ADC_SC3_CAL_MASK 0x80u
443 #define ADC_SC3_CAL_SHIFT 7
444 #define ADC_SC3_CAL_WIDTH 1
445 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
446 /* OFS Bit Fields */
447 #define ADC_OFS_OFS_MASK 0xFFFFu
448 #define ADC_OFS_OFS_SHIFT 0
449 #define ADC_OFS_OFS_WIDTH 16
450 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
451 /* PG Bit Fields */
452 #define ADC_PG_PG_MASK 0xFFFFu
453 #define ADC_PG_PG_SHIFT 0
454 #define ADC_PG_PG_WIDTH 16
455 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
456 /* MG Bit Fields */
457 #define ADC_MG_MG_MASK 0xFFFFu
458 #define ADC_MG_MG_SHIFT 0
459 #define ADC_MG_MG_WIDTH 16
460 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
461 /* CLPD Bit Fields */
462 #define ADC_CLPD_CLPD_MASK 0x3Fu
463 #define ADC_CLPD_CLPD_SHIFT 0
464 #define ADC_CLPD_CLPD_WIDTH 6
465 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
466 /* CLPS Bit Fields */
467 #define ADC_CLPS_CLPS_MASK 0x3Fu
468 #define ADC_CLPS_CLPS_SHIFT 0
469 #define ADC_CLPS_CLPS_WIDTH 6
470 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
471 /* CLP4 Bit Fields */
472 #define ADC_CLP4_CLP4_MASK 0x3FFu
473 #define ADC_CLP4_CLP4_SHIFT 0
474 #define ADC_CLP4_CLP4_WIDTH 10
475 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
476 /* CLP3 Bit Fields */
477 #define ADC_CLP3_CLP3_MASK 0x1FFu
478 #define ADC_CLP3_CLP3_SHIFT 0
479 #define ADC_CLP3_CLP3_WIDTH 9
480 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
481 /* CLP2 Bit Fields */
482 #define ADC_CLP2_CLP2_MASK 0xFFu
483 #define ADC_CLP2_CLP2_SHIFT 0
484 #define ADC_CLP2_CLP2_WIDTH 8
485 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
486 /* CLP1 Bit Fields */
487 #define ADC_CLP1_CLP1_MASK 0x7Fu
488 #define ADC_CLP1_CLP1_SHIFT 0
489 #define ADC_CLP1_CLP1_WIDTH 7
490 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
491 /* CLP0 Bit Fields */
492 #define ADC_CLP0_CLP0_MASK 0x3Fu
493 #define ADC_CLP0_CLP0_SHIFT 0
494 #define ADC_CLP0_CLP0_WIDTH 6
495 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
496 /* CLMD Bit Fields */
497 #define ADC_CLMD_CLMD_MASK 0x3Fu
498 #define ADC_CLMD_CLMD_SHIFT 0
499 #define ADC_CLMD_CLMD_WIDTH 6
500 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
501 /* CLMS Bit Fields */
502 #define ADC_CLMS_CLMS_MASK 0x3Fu
503 #define ADC_CLMS_CLMS_SHIFT 0
504 #define ADC_CLMS_CLMS_WIDTH 6
505 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
506 /* CLM4 Bit Fields */
507 #define ADC_CLM4_CLM4_MASK 0x3FFu
508 #define ADC_CLM4_CLM4_SHIFT 0
509 #define ADC_CLM4_CLM4_WIDTH 10
510 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
511 /* CLM3 Bit Fields */
512 #define ADC_CLM3_CLM3_MASK 0x1FFu
513 #define ADC_CLM3_CLM3_SHIFT 0
514 #define ADC_CLM3_CLM3_WIDTH 9
515 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
516 /* CLM2 Bit Fields */
517 #define ADC_CLM2_CLM2_MASK 0xFFu
518 #define ADC_CLM2_CLM2_SHIFT 0
519 #define ADC_CLM2_CLM2_WIDTH 8
520 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
521 /* CLM1 Bit Fields */
522 #define ADC_CLM1_CLM1_MASK 0x7Fu
523 #define ADC_CLM1_CLM1_SHIFT 0
524 #define ADC_CLM1_CLM1_WIDTH 7
525 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
526 /* CLM0 Bit Fields */
527 #define ADC_CLM0_CLM0_MASK 0x3Fu
528 #define ADC_CLM0_CLM0_SHIFT 0
529 #define ADC_CLM0_CLM0_WIDTH 6
530 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
531 
532 /*!
533  * @}
534  */ /* end of group ADC_Register_Masks */
535 
536 
537 /* ADC - Peripheral instance base addresses */
538 /** Peripheral ADC0 base address */
539 #define ADC0_BASE (0x4003B000u)
540 /** Peripheral ADC0 base pointer */
541 #define ADC0 ((ADC_Type *)ADC0_BASE)
542 #define ADC0_BASE_PTR (ADC0)
543 /** Array initializer of ADC peripheral base addresses */
544 #define ADC_BASE_ADDRS { ADC0_BASE }
545 /** Array initializer of ADC peripheral base pointers */
546 #define ADC_BASE_PTRS { ADC0 }
547 /** Interrupt vectors for the ADC peripheral type */
548 #define ADC_IRQS { ADC0_IRQn }
549 
550 /* ----------------------------------------------------------------------------
551  -- ADC - Register accessor macros
552  ---------------------------------------------------------------------------- */
553 
554 /*!
555  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
556  * @{
557  */
558 
559 
560 /* ADC - Register instance definitions */
561 /* ADC0 */
562 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
563 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
564 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
565 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
566 #define ADC0_RA ADC_R_REG(ADC0,0)
567 #define ADC0_RB ADC_R_REG(ADC0,1)
568 #define ADC0_CV1 ADC_CV1_REG(ADC0)
569 #define ADC0_CV2 ADC_CV2_REG(ADC0)
570 #define ADC0_SC2 ADC_SC2_REG(ADC0)
571 #define ADC0_SC3 ADC_SC3_REG(ADC0)
572 #define ADC0_OFS ADC_OFS_REG(ADC0)
573 #define ADC0_PG ADC_PG_REG(ADC0)
574 #define ADC0_MG ADC_MG_REG(ADC0)
575 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
576 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
577 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
578 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
579 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
580 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
581 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
582 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
583 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
584 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
585 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
586 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
587 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
588 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
589 
590 /* ADC - Register array accessors */
591 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
592 #define ADC0_R(index) ADC_R_REG(ADC0,index)
593 
594 /*!
595  * @}
596  */ /* end of group ADC_Register_Accessor_Macros */
597 
598 
599 /*!
600  * @}
601  */ /* end of group ADC_Peripheral_Access_Layer */
602 
603 
604 /* ----------------------------------------------------------------------------
605  -- CMP Peripheral Access Layer
606  ---------------------------------------------------------------------------- */
607 
608 /*!
609  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
610  * @{
611  */
612 
613 /** CMP - Register Layout Typedef */
614 typedef struct {
615  __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
616  __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
617  __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
618  __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
619  __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
620  __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
621 } CMP_Type, *CMP_MemMapPtr;
622 
623 /* ----------------------------------------------------------------------------
624  -- CMP - Register accessor macros
625  ---------------------------------------------------------------------------- */
626 
627 /*!
628  * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
629  * @{
630  */
631 
632 
633 /* CMP - Register accessors */
634 #define CMP_CR0_REG(base) ((base)->CR0)
635 #define CMP_CR1_REG(base) ((base)->CR1)
636 #define CMP_FPR_REG(base) ((base)->FPR)
637 #define CMP_SCR_REG(base) ((base)->SCR)
638 #define CMP_DACCR_REG(base) ((base)->DACCR)
639 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
640 
641 /*!
642  * @}
643  */ /* end of group CMP_Register_Accessor_Macros */
644 
645 
646 /* ----------------------------------------------------------------------------
647  -- CMP Register Masks
648  ---------------------------------------------------------------------------- */
649 
650 /*!
651  * @addtogroup CMP_Register_Masks CMP Register Masks
652  * @{
653  */
654 
655 /* CR0 Bit Fields */
656 #define CMP_CR0_HYSTCTR_MASK 0x3u
657 #define CMP_CR0_HYSTCTR_SHIFT 0
658 #define CMP_CR0_HYSTCTR_WIDTH 2
659 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
660 #define CMP_CR0_FILTER_CNT_MASK 0x70u
661 #define CMP_CR0_FILTER_CNT_SHIFT 4
662 #define CMP_CR0_FILTER_CNT_WIDTH 3
663 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
664 /* CR1 Bit Fields */
665 #define CMP_CR1_EN_MASK 0x1u
666 #define CMP_CR1_EN_SHIFT 0
667 #define CMP_CR1_EN_WIDTH 1
668 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
669 #define CMP_CR1_OPE_MASK 0x2u
670 #define CMP_CR1_OPE_SHIFT 1
671 #define CMP_CR1_OPE_WIDTH 1
672 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
673 #define CMP_CR1_COS_MASK 0x4u
674 #define CMP_CR1_COS_SHIFT 2
675 #define CMP_CR1_COS_WIDTH 1
676 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
677 #define CMP_CR1_INV_MASK 0x8u
678 #define CMP_CR1_INV_SHIFT 3
679 #define CMP_CR1_INV_WIDTH 1
680 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
681 #define CMP_CR1_PMODE_MASK 0x10u
682 #define CMP_CR1_PMODE_SHIFT 4
683 #define CMP_CR1_PMODE_WIDTH 1
684 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
685 #define CMP_CR1_TRIGM_MASK 0x20u
686 #define CMP_CR1_TRIGM_SHIFT 5
687 #define CMP_CR1_TRIGM_WIDTH 1
688 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
689 #define CMP_CR1_WE_MASK 0x40u
690 #define CMP_CR1_WE_SHIFT 6
691 #define CMP_CR1_WE_WIDTH 1
692 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
693 #define CMP_CR1_SE_MASK 0x80u
694 #define CMP_CR1_SE_SHIFT 7
695 #define CMP_CR1_SE_WIDTH 1
696 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
697 /* FPR Bit Fields */
698 #define CMP_FPR_FILT_PER_MASK 0xFFu
699 #define CMP_FPR_FILT_PER_SHIFT 0
700 #define CMP_FPR_FILT_PER_WIDTH 8
701 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
702 /* SCR Bit Fields */
703 #define CMP_SCR_COUT_MASK 0x1u
704 #define CMP_SCR_COUT_SHIFT 0
705 #define CMP_SCR_COUT_WIDTH 1
706 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
707 #define CMP_SCR_CFF_MASK 0x2u
708 #define CMP_SCR_CFF_SHIFT 1
709 #define CMP_SCR_CFF_WIDTH 1
710 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
711 #define CMP_SCR_CFR_MASK 0x4u
712 #define CMP_SCR_CFR_SHIFT 2
713 #define CMP_SCR_CFR_WIDTH 1
714 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
715 #define CMP_SCR_IEF_MASK 0x8u
716 #define CMP_SCR_IEF_SHIFT 3
717 #define CMP_SCR_IEF_WIDTH 1
718 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
719 #define CMP_SCR_IER_MASK 0x10u
720 #define CMP_SCR_IER_SHIFT 4
721 #define CMP_SCR_IER_WIDTH 1
722 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
723 #define CMP_SCR_DMAEN_MASK 0x40u
724 #define CMP_SCR_DMAEN_SHIFT 6
725 #define CMP_SCR_DMAEN_WIDTH 1
726 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
727 /* DACCR Bit Fields */
728 #define CMP_DACCR_VOSEL_MASK 0x3Fu
729 #define CMP_DACCR_VOSEL_SHIFT 0
730 #define CMP_DACCR_VOSEL_WIDTH 6
731 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
732 #define CMP_DACCR_VRSEL_MASK 0x40u
733 #define CMP_DACCR_VRSEL_SHIFT 6
734 #define CMP_DACCR_VRSEL_WIDTH 1
735 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
736 #define CMP_DACCR_DACEN_MASK 0x80u
737 #define CMP_DACCR_DACEN_SHIFT 7
738 #define CMP_DACCR_DACEN_WIDTH 1
739 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
740 /* MUXCR Bit Fields */
741 #define CMP_MUXCR_MSEL_MASK 0x7u
742 #define CMP_MUXCR_MSEL_SHIFT 0
743 #define CMP_MUXCR_MSEL_WIDTH 3
744 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
745 #define CMP_MUXCR_PSEL_MASK 0x38u
746 #define CMP_MUXCR_PSEL_SHIFT 3
747 #define CMP_MUXCR_PSEL_WIDTH 3
748 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
749 #define CMP_MUXCR_PSTM_MASK 0x80u
750 #define CMP_MUXCR_PSTM_SHIFT 7
751 #define CMP_MUXCR_PSTM_WIDTH 1
752 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
753 
754 /*!
755  * @}
756  */ /* end of group CMP_Register_Masks */
757 
758 
759 /* CMP - Peripheral instance base addresses */
760 /** Peripheral CMP0 base address */
761 #define CMP0_BASE (0x40073000u)
762 /** Peripheral CMP0 base pointer */
763 #define CMP0 ((CMP_Type *)CMP0_BASE)
764 #define CMP0_BASE_PTR (CMP0)
765 /** Array initializer of CMP peripheral base addresses */
766 #define CMP_BASE_ADDRS { CMP0_BASE }
767 /** Array initializer of CMP peripheral base pointers */
768 #define CMP_BASE_PTRS { CMP0 }
769 /** Interrupt vectors for the CMP peripheral type */
770 #define CMP_IRQS { CMP0_IRQn }
771 
772 /* ----------------------------------------------------------------------------
773  -- CMP - Register accessor macros
774  ---------------------------------------------------------------------------- */
775 
776 /*!
777  * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
778  * @{
779  */
780 
781 
782 /* CMP - Register instance definitions */
783 /* CMP0 */
784 #define CMP0_CR0 CMP_CR0_REG(CMP0)
785 #define CMP0_CR1 CMP_CR1_REG(CMP0)
786 #define CMP0_FPR CMP_FPR_REG(CMP0)
787 #define CMP0_SCR CMP_SCR_REG(CMP0)
788 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
789 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
790 
791 /*!
792  * @}
793  */ /* end of group CMP_Register_Accessor_Macros */
794 
795 
796 /*!
797  * @}
798  */ /* end of group CMP_Peripheral_Access_Layer */
799 
800 
801 /* ----------------------------------------------------------------------------
802  -- DAC Peripheral Access Layer
803  ---------------------------------------------------------------------------- */
804 
805 /*!
806  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
807  * @{
808  */
809 
810 /** DAC - Register Layout Typedef */
811 typedef struct {
812  struct { /* offset: 0x0, array step: 0x2 */
813  __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
814  __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
815  } DAT[2];
816  uint8_t RESERVED_0[28];
817  __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
818  __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
819  __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
820  __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
821 } DAC_Type, *DAC_MemMapPtr;
822 
823 /* ----------------------------------------------------------------------------
824  -- DAC - Register accessor macros
825  ---------------------------------------------------------------------------- */
826 
827 /*!
828  * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
829  * @{
830  */
831 
832 
833 /* DAC - Register accessors */
834 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
835 #define DAC_DATL_COUNT 2
836 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
837 #define DAC_DATH_COUNT 2
838 #define DAC_SR_REG(base) ((base)->SR)
839 #define DAC_C0_REG(base) ((base)->C0)
840 #define DAC_C1_REG(base) ((base)->C1)
841 #define DAC_C2_REG(base) ((base)->C2)
842 
843 /*!
844  * @}
845  */ /* end of group DAC_Register_Accessor_Macros */
846 
847 
848 /* ----------------------------------------------------------------------------
849  -- DAC Register Masks
850  ---------------------------------------------------------------------------- */
851 
852 /*!
853  * @addtogroup DAC_Register_Masks DAC Register Masks
854  * @{
855  */
856 
857 /* DATL Bit Fields */
858 #define DAC_DATL_DATA0_MASK 0xFFu
859 #define DAC_DATL_DATA0_SHIFT 0
860 #define DAC_DATL_DATA0_WIDTH 8
861 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
862 /* DATH Bit Fields */
863 #define DAC_DATH_DATA1_MASK 0xFu
864 #define DAC_DATH_DATA1_SHIFT 0
865 #define DAC_DATH_DATA1_WIDTH 4
866 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
867 /* SR Bit Fields */
868 #define DAC_SR_DACBFRPBF_MASK 0x1u
869 #define DAC_SR_DACBFRPBF_SHIFT 0
870 #define DAC_SR_DACBFRPBF_WIDTH 1
871 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
872 #define DAC_SR_DACBFRPTF_MASK 0x2u
873 #define DAC_SR_DACBFRPTF_SHIFT 1
874 #define DAC_SR_DACBFRPTF_WIDTH 1
875 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
876 /* C0 Bit Fields */
877 #define DAC_C0_DACBBIEN_MASK 0x1u
878 #define DAC_C0_DACBBIEN_SHIFT 0
879 #define DAC_C0_DACBBIEN_WIDTH 1
880 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
881 #define DAC_C0_DACBTIEN_MASK 0x2u
882 #define DAC_C0_DACBTIEN_SHIFT 1
883 #define DAC_C0_DACBTIEN_WIDTH 1
884 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
885 #define DAC_C0_LPEN_MASK 0x8u
886 #define DAC_C0_LPEN_SHIFT 3
887 #define DAC_C0_LPEN_WIDTH 1
888 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
889 #define DAC_C0_DACSWTRG_MASK 0x10u
890 #define DAC_C0_DACSWTRG_SHIFT 4
891 #define DAC_C0_DACSWTRG_WIDTH 1
892 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
893 #define DAC_C0_DACTRGSEL_MASK 0x20u
894 #define DAC_C0_DACTRGSEL_SHIFT 5
895 #define DAC_C0_DACTRGSEL_WIDTH 1
896 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
897 #define DAC_C0_DACRFS_MASK 0x40u
898 #define DAC_C0_DACRFS_SHIFT 6
899 #define DAC_C0_DACRFS_WIDTH 1
900 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
901 #define DAC_C0_DACEN_MASK 0x80u
902 #define DAC_C0_DACEN_SHIFT 7
903 #define DAC_C0_DACEN_WIDTH 1
904 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
905 /* C1 Bit Fields */
906 #define DAC_C1_DACBFEN_MASK 0x1u
907 #define DAC_C1_DACBFEN_SHIFT 0
908 #define DAC_C1_DACBFEN_WIDTH 1
909 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
910 #define DAC_C1_DACBFMD_MASK 0x4u
911 #define DAC_C1_DACBFMD_SHIFT 2
912 #define DAC_C1_DACBFMD_WIDTH 1
913 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
914 #define DAC_C1_DMAEN_MASK 0x80u
915 #define DAC_C1_DMAEN_SHIFT 7
916 #define DAC_C1_DMAEN_WIDTH 1
917 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
918 /* C2 Bit Fields */
919 #define DAC_C2_DACBFUP_MASK 0x1u
920 #define DAC_C2_DACBFUP_SHIFT 0
921 #define DAC_C2_DACBFUP_WIDTH 1
922 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
923 #define DAC_C2_DACBFRP_MASK 0x10u
924 #define DAC_C2_DACBFRP_SHIFT 4
925 #define DAC_C2_DACBFRP_WIDTH 1
926 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
927 
928 /*!
929  * @}
930  */ /* end of group DAC_Register_Masks */
931 
932 
933 /* DAC - Peripheral instance base addresses */
934 /** Peripheral DAC0 base address */
935 #define DAC0_BASE (0x4003F000u)
936 /** Peripheral DAC0 base pointer */
937 #define DAC0 ((DAC_Type *)DAC0_BASE)
938 #define DAC0_BASE_PTR (DAC0)
939 /** Array initializer of DAC peripheral base addresses */
940 #define DAC_BASE_ADDRS { DAC0_BASE }
941 /** Array initializer of DAC peripheral base pointers */
942 #define DAC_BASE_PTRS { DAC0 }
943 /** Interrupt vectors for the DAC peripheral type */
944 #define DAC_IRQS { DAC0_IRQn }
945 
946 /* ----------------------------------------------------------------------------
947  -- DAC - Register accessor macros
948  ---------------------------------------------------------------------------- */
949 
950 /*!
951  * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
952  * @{
953  */
954 
955 
956 /* DAC - Register instance definitions */
957 /* DAC0 */
958 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
959 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
960 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
961 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
962 #define DAC0_SR DAC_SR_REG(DAC0)
963 #define DAC0_C0 DAC_C0_REG(DAC0)
964 #define DAC0_C1 DAC_C1_REG(DAC0)
965 #define DAC0_C2 DAC_C2_REG(DAC0)
966 
967 /* DAC - Register array accessors */
968 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
969 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
970 
971 /*!
972  * @}
973  */ /* end of group DAC_Register_Accessor_Macros */
974 
975 
976 /*!
977  * @}
978  */ /* end of group DAC_Peripheral_Access_Layer */
979 
980 
981 /* ----------------------------------------------------------------------------
982  -- DMA Peripheral Access Layer
983  ---------------------------------------------------------------------------- */
984 
985 /*!
986  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
987  * @{
988  */
989 
990 /** DMA - Register Layout Typedef */
991 typedef struct {
992  uint8_t RESERVED_0[256];
993  struct { /* offset: 0x100, array step: 0x10 */
994  __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
995  __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
996  union { /* offset: 0x108, array step: 0x10 */
997  __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
998  struct { /* offset: 0x108, array step: 0x10 */
999  uint8_t RESERVED_0[3];
1000  __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
1001  } DMA_DSR_ACCESS8BIT;
1002  };
1003  __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
1004  } DMA[4];
1005 } DMA_Type, *DMA_MemMapPtr;
1006 
1007 /* ----------------------------------------------------------------------------
1008  -- DMA - Register accessor macros
1009  ---------------------------------------------------------------------------- */
1010 
1011 /*!
1012  * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
1013  * @{
1014  */
1015 
1016 
1017 /* DMA - Register accessors */
1018 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
1019 #define DMA_SAR_COUNT 4
1020 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
1021 #define DMA_DAR_COUNT 4
1022 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
1023 #define DMA_DSR_BCR_COUNT 4
1024 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
1025 #define DMA_DSR_COUNT 4
1026 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
1027 #define DMA_DCR_COUNT 4
1028 
1029 /*!
1030  * @}
1031  */ /* end of group DMA_Register_Accessor_Macros */
1032 
1033 
1034 /* ----------------------------------------------------------------------------
1035  -- DMA Register Masks
1036  ---------------------------------------------------------------------------- */
1037 
1038 /*!
1039  * @addtogroup DMA_Register_Masks DMA Register Masks
1040  * @{
1041  */
1042 
1043 /* SAR Bit Fields */
1044 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
1045 #define DMA_SAR_SAR_SHIFT 0
1046 #define DMA_SAR_SAR_WIDTH 32
1047 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
1048 /* DAR Bit Fields */
1049 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
1050 #define DMA_DAR_DAR_SHIFT 0
1051 #define DMA_DAR_DAR_WIDTH 32
1052 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
1053 /* DSR_BCR Bit Fields */
1054 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
1055 #define DMA_DSR_BCR_BCR_SHIFT 0
1056 #define DMA_DSR_BCR_BCR_WIDTH 24
1057 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
1058 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
1059 #define DMA_DSR_BCR_DONE_SHIFT 24
1060 #define DMA_DSR_BCR_DONE_WIDTH 1
1061 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_DONE_SHIFT))&DMA_DSR_BCR_DONE_MASK)
1062 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
1063 #define DMA_DSR_BCR_BSY_SHIFT 25
1064 #define DMA_DSR_BCR_BSY_WIDTH 1
1065 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BSY_SHIFT))&DMA_DSR_BCR_BSY_MASK)
1066 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
1067 #define DMA_DSR_BCR_REQ_SHIFT 26
1068 #define DMA_DSR_BCR_REQ_WIDTH 1
1069 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_REQ_SHIFT))&DMA_DSR_BCR_REQ_MASK)
1070 #define DMA_DSR_BCR_BED_MASK 0x10000000u
1071 #define DMA_DSR_BCR_BED_SHIFT 28
1072 #define DMA_DSR_BCR_BED_WIDTH 1
1073 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BED_SHIFT))&DMA_DSR_BCR_BED_MASK)
1074 #define DMA_DSR_BCR_BES_MASK 0x20000000u
1075 #define DMA_DSR_BCR_BES_SHIFT 29
1076 #define DMA_DSR_BCR_BES_WIDTH 1
1077 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BES_SHIFT))&DMA_DSR_BCR_BES_MASK)
1078 #define DMA_DSR_BCR_CE_MASK 0x40000000u
1079 #define DMA_DSR_BCR_CE_SHIFT 30
1080 #define DMA_DSR_BCR_CE_WIDTH 1
1081 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_CE_SHIFT))&DMA_DSR_BCR_CE_MASK)
1082 /* DCR Bit Fields */
1083 #define DMA_DCR_LCH2_MASK 0x3u
1084 #define DMA_DCR_LCH2_SHIFT 0
1085 #define DMA_DCR_LCH2_WIDTH 2
1086 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
1087 #define DMA_DCR_LCH1_MASK 0xCu
1088 #define DMA_DCR_LCH1_SHIFT 2
1089 #define DMA_DCR_LCH1_WIDTH 2
1090 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
1091 #define DMA_DCR_LINKCC_MASK 0x30u
1092 #define DMA_DCR_LINKCC_SHIFT 4
1093 #define DMA_DCR_LINKCC_WIDTH 2
1094 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
1095 #define DMA_DCR_D_REQ_MASK 0x80u
1096 #define DMA_DCR_D_REQ_SHIFT 7
1097 #define DMA_DCR_D_REQ_WIDTH 1
1098 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_D_REQ_SHIFT))&DMA_DCR_D_REQ_MASK)
1099 #define DMA_DCR_DMOD_MASK 0xF00u
1100 #define DMA_DCR_DMOD_SHIFT 8
1101 #define DMA_DCR_DMOD_WIDTH 4
1102 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
1103 #define DMA_DCR_SMOD_MASK 0xF000u
1104 #define DMA_DCR_SMOD_SHIFT 12
1105 #define DMA_DCR_SMOD_WIDTH 4
1106 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
1107 #define DMA_DCR_START_MASK 0x10000u
1108 #define DMA_DCR_START_SHIFT 16
1109 #define DMA_DCR_START_WIDTH 1
1110 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_START_SHIFT))&DMA_DCR_START_MASK)
1111 #define DMA_DCR_DSIZE_MASK 0x60000u
1112 #define DMA_DCR_DSIZE_SHIFT 17
1113 #define DMA_DCR_DSIZE_WIDTH 2
1114 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
1115 #define DMA_DCR_DINC_MASK 0x80000u
1116 #define DMA_DCR_DINC_SHIFT 19
1117 #define DMA_DCR_DINC_WIDTH 1
1118 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DINC_SHIFT))&DMA_DCR_DINC_MASK)
1119 #define DMA_DCR_SSIZE_MASK 0x300000u
1120 #define DMA_DCR_SSIZE_SHIFT 20
1121 #define DMA_DCR_SSIZE_WIDTH 2
1122 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
1123 #define DMA_DCR_SINC_MASK 0x400000u
1124 #define DMA_DCR_SINC_SHIFT 22
1125 #define DMA_DCR_SINC_WIDTH 1
1126 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SINC_SHIFT))&DMA_DCR_SINC_MASK)
1127 #define DMA_DCR_EADREQ_MASK 0x800000u
1128 #define DMA_DCR_EADREQ_SHIFT 23
1129 #define DMA_DCR_EADREQ_WIDTH 1
1130 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_EADREQ_SHIFT))&DMA_DCR_EADREQ_MASK)
1131 #define DMA_DCR_AA_MASK 0x10000000u
1132 #define DMA_DCR_AA_SHIFT 28
1133 #define DMA_DCR_AA_WIDTH 1
1134 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_AA_SHIFT))&DMA_DCR_AA_MASK)
1135 #define DMA_DCR_CS_MASK 0x20000000u
1136 #define DMA_DCR_CS_SHIFT 29
1137 #define DMA_DCR_CS_WIDTH 1
1138 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_CS_SHIFT))&DMA_DCR_CS_MASK)
1139 #define DMA_DCR_ERQ_MASK 0x40000000u
1140 #define DMA_DCR_ERQ_SHIFT 30
1141 #define DMA_DCR_ERQ_WIDTH 1
1142 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_ERQ_SHIFT))&DMA_DCR_ERQ_MASK)
1143 #define DMA_DCR_EINT_MASK 0x80000000u
1144 #define DMA_DCR_EINT_SHIFT 31
1145 #define DMA_DCR_EINT_WIDTH 1
1146 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_EINT_SHIFT))&DMA_DCR_EINT_MASK)
1147 
1148 /*!
1149  * @}
1150  */ /* end of group DMA_Register_Masks */
1151 
1152 
1153 /* DMA - Peripheral instance base addresses */
1154 /** Peripheral DMA base address */
1155 #define DMA_BASE (0x40008000u)
1156 /** Peripheral DMA base pointer */
1157 #define DMA0 ((DMA_Type *)DMA_BASE)
1158 #define DMA_BASE_PTR (DMA0)
1159 /** Array initializer of DMA peripheral base addresses */
1160 #define DMA_BASE_ADDRS { DMA_BASE }
1161 /** Array initializer of DMA peripheral base pointers */
1162 #define DMA_BASE_PTRS { DMA0 }
1163 /** Interrupt vectors for the DMA peripheral type */
1164 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
1165 
1166 /* ----------------------------------------------------------------------------
1167  -- DMA - Register accessor macros
1168  ---------------------------------------------------------------------------- */
1169 
1170 /*!
1171  * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
1172  * @{
1173  */
1174 
1175 
1176 /* DMA - Register instance definitions */
1177 /* DMA */
1178 #define DMA_SAR0 DMA_SAR_REG(DMA0,0)
1179 #define DMA_DAR0 DMA_DAR_REG(DMA0,0)
1180 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
1181 #define DMA_DSR0 DMA_DSR_REG(DMA0,0)
1182 #define DMA_DCR0 DMA_DCR_REG(DMA0,0)
1183 #define DMA_SAR1 DMA_SAR_REG(DMA0,1)
1184 #define DMA_DAR1 DMA_DAR_REG(DMA0,1)
1185 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
1186 #define DMA_DSR1 DMA_DSR_REG(DMA0,1)
1187 #define DMA_DCR1 DMA_DCR_REG(DMA0,1)
1188 #define DMA_SAR2 DMA_SAR_REG(DMA0,2)
1189 #define DMA_DAR2 DMA_DAR_REG(DMA0,2)
1190 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
1191 #define DMA_DSR2 DMA_DSR_REG(DMA0,2)
1192 #define DMA_DCR2 DMA_DCR_REG(DMA0,2)
1193 #define DMA_SAR3 DMA_SAR_REG(DMA0,3)
1194 #define DMA_DAR3 DMA_DAR_REG(DMA0,3)
1195 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
1196 #define DMA_DSR3 DMA_DSR_REG(DMA0,3)
1197 #define DMA_DCR3 DMA_DCR_REG(DMA0,3)
1198 
1199 /* DMA - Register array accessors */
1200 #define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
1201 #define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
1202 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
1203 #define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
1204 #define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
1205 
1206 /*!
1207  * @}
1208  */ /* end of group DMA_Register_Accessor_Macros */
1209 
1210 
1211 /*!
1212  * @}
1213  */ /* end of group DMA_Peripheral_Access_Layer */
1214 
1215 
1216 /* ----------------------------------------------------------------------------
1217  -- DMAMUX Peripheral Access Layer
1218  ---------------------------------------------------------------------------- */
1219 
1220 /*!
1221  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1222  * @{
1223  */
1224 
1225 /** DMAMUX - Register Layout Typedef */
1226 typedef struct {
1227  __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
1228 } DMAMUX_Type, *DMAMUX_MemMapPtr;
1229 
1230 /* ----------------------------------------------------------------------------
1231  -- DMAMUX - Register accessor macros
1232  ---------------------------------------------------------------------------- */
1233 
1234 /*!
1235  * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
1236  * @{
1237  */
1238 
1239 
1240 /* DMAMUX - Register accessors */
1241 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
1242 #define DMAMUX_CHCFG_COUNT 4
1243 
1244 /*!
1245  * @}
1246  */ /* end of group DMAMUX_Register_Accessor_Macros */
1247 
1248 
1249 /* ----------------------------------------------------------------------------
1250  -- DMAMUX Register Masks
1251  ---------------------------------------------------------------------------- */
1252 
1253 /*!
1254  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1255  * @{
1256  */
1257 
1258 /* CHCFG Bit Fields */
1259 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
1260 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
1261 #define DMAMUX_CHCFG_SOURCE_WIDTH 6
1262 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
1263 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
1264 #define DMAMUX_CHCFG_TRIG_SHIFT 6
1265 #define DMAMUX_CHCFG_TRIG_WIDTH 1
1266 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
1267 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
1268 #define DMAMUX_CHCFG_ENBL_SHIFT 7
1269 #define DMAMUX_CHCFG_ENBL_WIDTH 1
1270 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
1271 
1272 /*!
1273  * @}
1274  */ /* end of group DMAMUX_Register_Masks */
1275 
1276 
1277 /* DMAMUX - Peripheral instance base addresses */
1278 /** Peripheral DMAMUX0 base address */
1279 #define DMAMUX0_BASE (0x40021000u)
1280 /** Peripheral DMAMUX0 base pointer */
1281 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
1282 #define DMAMUX0_BASE_PTR (DMAMUX0)
1283 /** Array initializer of DMAMUX peripheral base addresses */
1284 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
1285 /** Array initializer of DMAMUX peripheral base pointers */
1286 #define DMAMUX_BASE_PTRS { DMAMUX0 }
1287 
1288 /* ----------------------------------------------------------------------------
1289  -- DMAMUX - Register accessor macros
1290  ---------------------------------------------------------------------------- */
1291 
1292 /*!
1293  * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
1294  * @{
1295  */
1296 
1297 
1298 /* DMAMUX - Register instance definitions */
1299 /* DMAMUX0 */
1300 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
1301 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
1302 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
1303 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
1304 
1305 /* DMAMUX - Register array accessors */
1306 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
1307 
1308 /*!
1309  * @}
1310  */ /* end of group DMAMUX_Register_Accessor_Macros */
1311 
1312 
1313 /*!
1314  * @}
1315  */ /* end of group DMAMUX_Peripheral_Access_Layer */
1316 
1317 
1318 /* ----------------------------------------------------------------------------
1319  -- FGPIO Peripheral Access Layer
1320  ---------------------------------------------------------------------------- */
1321 
1322 /*!
1323  * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
1324  * @{
1325  */
1326 
1327 /** FGPIO - Register Layout Typedef */
1328 typedef struct {
1329  __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1330  __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1331  __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1332  __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1333  __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1334  __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1335 } FGPIO_Type, *FGPIO_MemMapPtr;
1336 
1337 /* ----------------------------------------------------------------------------
1338  -- FGPIO - Register accessor macros
1339  ---------------------------------------------------------------------------- */
1340 
1341 /*!
1342  * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
1343  * @{
1344  */
1345 
1346 
1347 /* FGPIO - Register accessors */
1348 #define FGPIO_PDOR_REG(base) ((base)->PDOR)
1349 #define FGPIO_PSOR_REG(base) ((base)->PSOR)
1350 #define FGPIO_PCOR_REG(base) ((base)->PCOR)
1351 #define FGPIO_PTOR_REG(base) ((base)->PTOR)
1352 #define FGPIO_PDIR_REG(base) ((base)->PDIR)
1353 #define FGPIO_PDDR_REG(base) ((base)->PDDR)
1354 
1355 /*!
1356  * @}
1357  */ /* end of group FGPIO_Register_Accessor_Macros */
1358 
1359 
1360 /* ----------------------------------------------------------------------------
1361  -- FGPIO Register Masks
1362  ---------------------------------------------------------------------------- */
1363 
1364 /*!
1365  * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
1366  * @{
1367  */
1368 
1369 /* PDOR Bit Fields */
1370 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
1371 #define FGPIO_PDOR_PDO_SHIFT 0
1372 #define FGPIO_PDOR_PDO_WIDTH 32
1373 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
1374 /* PSOR Bit Fields */
1375 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
1376 #define FGPIO_PSOR_PTSO_SHIFT 0
1377 #define FGPIO_PSOR_PTSO_WIDTH 32
1378 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
1379 /* PCOR Bit Fields */
1380 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
1381 #define FGPIO_PCOR_PTCO_SHIFT 0
1382 #define FGPIO_PCOR_PTCO_WIDTH 32
1383 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
1384 /* PTOR Bit Fields */
1385 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
1386 #define FGPIO_PTOR_PTTO_SHIFT 0
1387 #define FGPIO_PTOR_PTTO_WIDTH 32
1388 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
1389 /* PDIR Bit Fields */
1390 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
1391 #define FGPIO_PDIR_PDI_SHIFT 0
1392 #define FGPIO_PDIR_PDI_WIDTH 32
1393 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
1394 /* PDDR Bit Fields */
1395 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
1396 #define FGPIO_PDDR_PDD_SHIFT 0
1397 #define FGPIO_PDDR_PDD_WIDTH 32
1398 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
1399 
1400 /*!
1401  * @}
1402  */ /* end of group FGPIO_Register_Masks */
1403 
1404 
1405 /* FGPIO - Peripheral instance base addresses */
1406 /** Peripheral FGPIOA base address */
1407 #define FGPIOA_BASE (0xF80FF000u)
1408 /** Peripheral FGPIOA base pointer */
1409 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
1410 #define FGPIOA_BASE_PTR (FGPIOA)
1411 /** Peripheral FGPIOB base address */
1412 #define FGPIOB_BASE (0xF80FF040u)
1413 /** Peripheral FGPIOB base pointer */
1414 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
1415 #define FGPIOB_BASE_PTR (FGPIOB)
1416 /** Peripheral FGPIOC base address */
1417 #define FGPIOC_BASE (0xF80FF080u)
1418 /** Peripheral FGPIOC base pointer */
1419 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
1420 #define FGPIOC_BASE_PTR (FGPIOC)
1421 /** Peripheral FGPIOD base address */
1422 #define FGPIOD_BASE (0xF80FF0C0u)
1423 /** Peripheral FGPIOD base pointer */
1424 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
1425 #define FGPIOD_BASE_PTR (FGPIOD)
1426 /** Peripheral FGPIOE base address */
1427 #define FGPIOE_BASE (0xF80FF100u)
1428 /** Peripheral FGPIOE base pointer */
1429 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
1430 #define FGPIOE_BASE_PTR (FGPIOE)
1431 /** Array initializer of FGPIO peripheral base addresses */
1432 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
1433 /** Array initializer of FGPIO peripheral base pointers */
1434 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
1435 
1436 /* ----------------------------------------------------------------------------
1437  -- FGPIO - Register accessor macros
1438  ---------------------------------------------------------------------------- */
1439 
1440 /*!
1441  * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
1442  * @{
1443  */
1444 
1445 
1446 /* FGPIO - Register instance definitions */
1447 /* FGPIOA */
1448 #define FGPIOA_PDOR FGPIO_PDOR_REG(FGPIOA)
1449 #define FGPIOA_PSOR FGPIO_PSOR_REG(FGPIOA)
1450 #define FGPIOA_PCOR FGPIO_PCOR_REG(FGPIOA)
1451 #define FGPIOA_PTOR FGPIO_PTOR_REG(FGPIOA)
1452 #define FGPIOA_PDIR FGPIO_PDIR_REG(FGPIOA)
1453 #define FGPIOA_PDDR FGPIO_PDDR_REG(FGPIOA)
1454 /* FGPIOB */
1455 #define FGPIOB_PDOR FGPIO_PDOR_REG(FGPIOB)
1456 #define FGPIOB_PSOR FGPIO_PSOR_REG(FGPIOB)
1457 #define FGPIOB_PCOR FGPIO_PCOR_REG(FGPIOB)
1458 #define FGPIOB_PTOR FGPIO_PTOR_REG(FGPIOB)
1459 #define FGPIOB_PDIR FGPIO_PDIR_REG(FGPIOB)
1460 #define FGPIOB_PDDR FGPIO_PDDR_REG(FGPIOB)
1461 /* FGPIOC */
1462 #define FGPIOC_PDOR FGPIO_PDOR_REG(FGPIOC)
1463 #define FGPIOC_PSOR FGPIO_PSOR_REG(FGPIOC)
1464 #define FGPIOC_PCOR FGPIO_PCOR_REG(FGPIOC)
1465 #define FGPIOC_PTOR FGPIO_PTOR_REG(FGPIOC)
1466 #define FGPIOC_PDIR FGPIO_PDIR_REG(FGPIOC)
1467 #define FGPIOC_PDDR FGPIO_PDDR_REG(FGPIOC)
1468 /* FGPIOD */
1469 #define FGPIOD_PDOR FGPIO_PDOR_REG(FGPIOD)
1470 #define FGPIOD_PSOR FGPIO_PSOR_REG(FGPIOD)
1471 #define FGPIOD_PCOR FGPIO_PCOR_REG(FGPIOD)
1472 #define FGPIOD_PTOR FGPIO_PTOR_REG(FGPIOD)
1473 #define FGPIOD_PDIR FGPIO_PDIR_REG(FGPIOD)
1474 #define FGPIOD_PDDR FGPIO_PDDR_REG(FGPIOD)
1475 /* FGPIOE */
1476 #define FGPIOE_PDOR FGPIO_PDOR_REG(FGPIOE)
1477 #define FGPIOE_PSOR FGPIO_PSOR_REG(FGPIOE)
1478 #define FGPIOE_PCOR FGPIO_PCOR_REG(FGPIOE)
1479 #define FGPIOE_PTOR FGPIO_PTOR_REG(FGPIOE)
1480 #define FGPIOE_PDIR FGPIO_PDIR_REG(FGPIOE)
1481 #define FGPIOE_PDDR FGPIO_PDDR_REG(FGPIOE)
1482 
1483 /*!
1484  * @}
1485  */ /* end of group FGPIO_Register_Accessor_Macros */
1486 
1487 
1488 /*!
1489  * @}
1490  */ /* end of group FGPIO_Peripheral_Access_Layer */
1491 
1492 
1493 /* ----------------------------------------------------------------------------
1494  -- FTFA Peripheral Access Layer
1495  ---------------------------------------------------------------------------- */
1496 
1497 /*!
1498  * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
1499  * @{
1500  */
1501 
1502 /** FTFA - Register Layout Typedef */
1503 typedef struct {
1504  __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
1505  __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
1506  __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
1507  __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
1508  __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
1509  __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
1510  __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
1511  __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
1512  __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
1513  __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
1514  __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
1515  __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
1516  __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
1517  __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
1518  __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
1519  __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
1520  __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
1521  __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
1522  __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
1523  __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
1524 } FTFA_Type, *FTFA_MemMapPtr;
1525 
1526 /* ----------------------------------------------------------------------------
1527  -- FTFA - Register accessor macros
1528  ---------------------------------------------------------------------------- */
1529 
1530 /*!
1531  * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
1532  * @{
1533  */
1534 
1535 
1536 /* FTFA - Register accessors */
1537 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
1538 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
1539 #define FTFA_FSEC_REG(base) ((base)->FSEC)
1540 #define FTFA_FOPT_REG(base) ((base)->FOPT)
1541 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
1542 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
1543 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
1544 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
1545 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
1546 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
1547 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
1548 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
1549 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
1550 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
1551 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
1552 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
1553 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
1554 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
1555 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
1556 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
1557 
1558 /*!
1559  * @}
1560  */ /* end of group FTFA_Register_Accessor_Macros */
1561 
1562 
1563 /* ----------------------------------------------------------------------------
1564  -- FTFA Register Masks
1565  ---------------------------------------------------------------------------- */
1566 
1567 /*!
1568  * @addtogroup FTFA_Register_Masks FTFA Register Masks
1569  * @{
1570  */
1571 
1572 /* FSTAT Bit Fields */
1573 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
1574 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
1575 #define FTFA_FSTAT_MGSTAT0_WIDTH 1
1576 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
1577 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
1578 #define FTFA_FSTAT_FPVIOL_SHIFT 4
1579 #define FTFA_FSTAT_FPVIOL_WIDTH 1
1580 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
1581 #define FTFA_FSTAT_ACCERR_MASK 0x20u
1582 #define FTFA_FSTAT_ACCERR_SHIFT 5
1583 #define FTFA_FSTAT_ACCERR_WIDTH 1
1584 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
1585 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
1586 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
1587 #define FTFA_FSTAT_RDCOLERR_WIDTH 1
1588 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
1589 #define FTFA_FSTAT_CCIF_MASK 0x80u
1590 #define FTFA_FSTAT_CCIF_SHIFT 7
1591 #define FTFA_FSTAT_CCIF_WIDTH 1
1592 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
1593 /* FCNFG Bit Fields */
1594 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
1595 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
1596 #define FTFA_FCNFG_ERSSUSP_WIDTH 1
1597 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
1598 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
1599 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
1600 #define FTFA_FCNFG_ERSAREQ_WIDTH 1
1601 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
1602 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
1603 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
1604 #define FTFA_FCNFG_RDCOLLIE_WIDTH 1
1605 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
1606 #define FTFA_FCNFG_CCIE_MASK 0x80u
1607 #define FTFA_FCNFG_CCIE_SHIFT 7
1608 #define FTFA_FCNFG_CCIE_WIDTH 1
1609 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
1610 /* FSEC Bit Fields */
1611 #define FTFA_FSEC_SEC_MASK 0x3u
1612 #define FTFA_FSEC_SEC_SHIFT 0
1613 #define FTFA_FSEC_SEC_WIDTH 2
1614 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
1615 #define FTFA_FSEC_FSLACC_MASK 0xCu
1616 #define FTFA_FSEC_FSLACC_SHIFT 2
1617 #define FTFA_FSEC_FSLACC_WIDTH 2
1618 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
1619 #define FTFA_FSEC_MEEN_MASK 0x30u
1620 #define FTFA_FSEC_MEEN_SHIFT 4
1621 #define FTFA_FSEC_MEEN_WIDTH 2
1622 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
1623 #define FTFA_FSEC_KEYEN_MASK 0xC0u
1624 #define FTFA_FSEC_KEYEN_SHIFT 6
1625 #define FTFA_FSEC_KEYEN_WIDTH 2
1626 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
1627 /* FOPT Bit Fields */
1628 #define FTFA_FOPT_OPT_MASK 0xFFu
1629 #define FTFA_FOPT_OPT_SHIFT 0
1630 #define FTFA_FOPT_OPT_WIDTH 8
1631 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
1632 /* FCCOB3 Bit Fields */
1633 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
1634 #define FTFA_FCCOB3_CCOBn_SHIFT 0
1635 #define FTFA_FCCOB3_CCOBn_WIDTH 8
1636 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
1637 /* FCCOB2 Bit Fields */
1638 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
1639 #define FTFA_FCCOB2_CCOBn_SHIFT 0
1640 #define FTFA_FCCOB2_CCOBn_WIDTH 8
1641 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
1642 /* FCCOB1 Bit Fields */
1643 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
1644 #define FTFA_FCCOB1_CCOBn_SHIFT 0
1645 #define FTFA_FCCOB1_CCOBn_WIDTH 8
1646 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
1647 /* FCCOB0 Bit Fields */
1648 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
1649 #define FTFA_FCCOB0_CCOBn_SHIFT 0
1650 #define FTFA_FCCOB0_CCOBn_WIDTH 8
1651 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
1652 /* FCCOB7 Bit Fields */
1653 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
1654 #define FTFA_FCCOB7_CCOBn_SHIFT 0
1655 #define FTFA_FCCOB7_CCOBn_WIDTH 8
1656 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
1657 /* FCCOB6 Bit Fields */
1658 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
1659 #define FTFA_FCCOB6_CCOBn_SHIFT 0
1660 #define FTFA_FCCOB6_CCOBn_WIDTH 8
1661 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
1662 /* FCCOB5 Bit Fields */
1663 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
1664 #define FTFA_FCCOB5_CCOBn_SHIFT 0
1665 #define FTFA_FCCOB5_CCOBn_WIDTH 8
1666 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
1667 /* FCCOB4 Bit Fields */
1668 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
1669 #define FTFA_FCCOB4_CCOBn_SHIFT 0
1670 #define FTFA_FCCOB4_CCOBn_WIDTH 8
1671 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
1672 /* FCCOBB Bit Fields */
1673 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
1674 #define FTFA_FCCOBB_CCOBn_SHIFT 0
1675 #define FTFA_FCCOBB_CCOBn_WIDTH 8
1676 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
1677 /* FCCOBA Bit Fields */
1678 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
1679 #define FTFA_FCCOBA_CCOBn_SHIFT 0
1680 #define FTFA_FCCOBA_CCOBn_WIDTH 8
1681 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
1682 /* FCCOB9 Bit Fields */
1683 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
1684 #define FTFA_FCCOB9_CCOBn_SHIFT 0
1685 #define FTFA_FCCOB9_CCOBn_WIDTH 8
1686 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
1687 /* FCCOB8 Bit Fields */
1688 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
1689 #define FTFA_FCCOB8_CCOBn_SHIFT 0
1690 #define FTFA_FCCOB8_CCOBn_WIDTH 8
1691 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
1692 /* FPROT3 Bit Fields */
1693 #define FTFA_FPROT3_PROT_MASK 0xFFu
1694 #define FTFA_FPROT3_PROT_SHIFT 0
1695 #define FTFA_FPROT3_PROT_WIDTH 8
1696 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
1697 /* FPROT2 Bit Fields */
1698 #define FTFA_FPROT2_PROT_MASK 0xFFu
1699 #define FTFA_FPROT2_PROT_SHIFT 0
1700 #define FTFA_FPROT2_PROT_WIDTH 8
1701 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
1702 /* FPROT1 Bit Fields */
1703 #define FTFA_FPROT1_PROT_MASK 0xFFu
1704 #define FTFA_FPROT1_PROT_SHIFT 0
1705 #define FTFA_FPROT1_PROT_WIDTH 8
1706 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
1707 /* FPROT0 Bit Fields */
1708 #define FTFA_FPROT0_PROT_MASK 0xFFu
1709 #define FTFA_FPROT0_PROT_SHIFT 0
1710 #define FTFA_FPROT0_PROT_WIDTH 8
1711 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
1712 
1713 /*!
1714  * @}
1715  */ /* end of group FTFA_Register_Masks */
1716 
1717 
1718 /* FTFA - Peripheral instance base addresses */
1719 /** Peripheral FTFA base address */
1720 #define FTFA_BASE (0x40020000u)
1721 /** Peripheral FTFA base pointer */
1722 #define FTFA ((FTFA_Type *)FTFA_BASE)
1723 #define FTFA_BASE_PTR (FTFA)
1724 /** Array initializer of FTFA peripheral base addresses */
1725 #define FTFA_BASE_ADDRS { FTFA_BASE }
1726 /** Array initializer of FTFA peripheral base pointers */
1727 #define FTFA_BASE_PTRS { FTFA }
1728 /** Interrupt vectors for the FTFA peripheral type */
1729 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
1730 
1731 /* ----------------------------------------------------------------------------
1732  -- FTFA - Register accessor macros
1733  ---------------------------------------------------------------------------- */
1734 
1735 /*!
1736  * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
1737  * @{
1738  */
1739 
1740 
1741 /* FTFA - Register instance definitions */
1742 /* FTFA */
1743 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
1744 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
1745 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
1746 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
1747 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
1748 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
1749 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
1750 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
1751 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
1752 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
1753 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
1754 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
1755 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
1756 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
1757 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
1758 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
1759 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
1760 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
1761 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
1762 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
1763 
1764 /*!
1765  * @}
1766  */ /* end of group FTFA_Register_Accessor_Macros */
1767 
1768 
1769 /*!
1770  * @}
1771  */ /* end of group FTFA_Peripheral_Access_Layer */
1772 
1773 
1774 /* ----------------------------------------------------------------------------
1775  -- GPIO Peripheral Access Layer
1776  ---------------------------------------------------------------------------- */
1777 
1778 /*!
1779  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1780  * @{
1781  */
1782 
1783 /** GPIO - Register Layout Typedef */
1784 typedef struct {
1785  __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1786  __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1787  __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1788  __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1789  __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1790  __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1791 } GPIO_Type, *GPIO_MemMapPtr;
1792 
1793 /* ----------------------------------------------------------------------------
1794  -- GPIO - Register accessor macros
1795  ---------------------------------------------------------------------------- */
1796 
1797 /*!
1798  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
1799  * @{
1800  */
1801 
1802 
1803 /* GPIO - Register accessors */
1804 #define GPIO_PDOR_REG(base) ((base)->PDOR)
1805 #define GPIO_PSOR_REG(base) ((base)->PSOR)
1806 #define GPIO_PCOR_REG(base) ((base)->PCOR)
1807 #define GPIO_PTOR_REG(base) ((base)->PTOR)
1808 #define GPIO_PDIR_REG(base) ((base)->PDIR)
1809 #define GPIO_PDDR_REG(base) ((base)->PDDR)
1810 
1811 /*!
1812  * @}
1813  */ /* end of group GPIO_Register_Accessor_Macros */
1814 
1815 
1816 /* ----------------------------------------------------------------------------
1817  -- GPIO Register Masks
1818  ---------------------------------------------------------------------------- */
1819 
1820 /*!
1821  * @addtogroup GPIO_Register_Masks GPIO Register Masks
1822  * @{
1823  */
1824 
1825 /* PDOR Bit Fields */
1826 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
1827 #define GPIO_PDOR_PDO_SHIFT 0
1828 #define GPIO_PDOR_PDO_WIDTH 32
1829 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
1830 /* PSOR Bit Fields */
1831 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
1832 #define GPIO_PSOR_PTSO_SHIFT 0
1833 #define GPIO_PSOR_PTSO_WIDTH 32
1834 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
1835 /* PCOR Bit Fields */
1836 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
1837 #define GPIO_PCOR_PTCO_SHIFT 0
1838 #define GPIO_PCOR_PTCO_WIDTH 32
1839 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
1840 /* PTOR Bit Fields */
1841 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
1842 #define GPIO_PTOR_PTTO_SHIFT 0
1843 #define GPIO_PTOR_PTTO_WIDTH 32
1844 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
1845 /* PDIR Bit Fields */
1846 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
1847 #define GPIO_PDIR_PDI_SHIFT 0
1848 #define GPIO_PDIR_PDI_WIDTH 32
1849 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
1850 /* PDDR Bit Fields */
1851 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
1852 #define GPIO_PDDR_PDD_SHIFT 0
1853 #define GPIO_PDDR_PDD_WIDTH 32
1854 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
1855 
1856 /*!
1857  * @}
1858  */ /* end of group GPIO_Register_Masks */
1859 
1860 
1861 /* GPIO - Peripheral instance base addresses */
1862 /** Peripheral GPIOA base address */
1863 #define GPIOA_BASE (0x400FF000u)
1864 /** Peripheral GPIOA base pointer */
1865 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
1866 #define GPIOA_BASE_PTR (GPIOA)
1867 /** Peripheral GPIOB base address */
1868 #define GPIOB_BASE (0x400FF040u)
1869 /** Peripheral GPIOB base pointer */
1870 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
1871 #define GPIOB_BASE_PTR (GPIOB)
1872 /** Peripheral GPIOC base address */
1873 #define GPIOC_BASE (0x400FF080u)
1874 /** Peripheral GPIOC base pointer */
1875 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
1876 #define GPIOC_BASE_PTR (GPIOC)
1877 /** Peripheral GPIOD base address */
1878 #define GPIOD_BASE (0x400FF0C0u)
1879 /** Peripheral GPIOD base pointer */
1880 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
1881 #define GPIOD_BASE_PTR (GPIOD)
1882 /** Peripheral GPIOE base address */
1883 #define GPIOE_BASE (0x400FF100u)
1884 /** Peripheral GPIOE base pointer */
1885 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
1886 #define GPIOE_BASE_PTR (GPIOE)
1887 /** Array initializer of GPIO peripheral base addresses */
1888 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
1889 /** Array initializer of GPIO peripheral base pointers */
1890 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
1891 
1892 /* ----------------------------------------------------------------------------
1893  -- GPIO - Register accessor macros
1894  ---------------------------------------------------------------------------- */
1895 
1896 /*!
1897  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
1898  * @{
1899  */
1900 
1901 
1902 /* GPIO - Register instance definitions */
1903 /* GPIOA */
1904 #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
1905 #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
1906 #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
1907 #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
1908 #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
1909 #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
1910 /* GPIOB */
1911 #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
1912 #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
1913 #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
1914 #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
1915 #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
1916 #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
1917 /* GPIOC */
1918 #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
1919 #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
1920 #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
1921 #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
1922 #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
1923 #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
1924 /* GPIOD */
1925 #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
1926 #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
1927 #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
1928 #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
1929 #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
1930 #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
1931 /* GPIOE */
1932 #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
1933 #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
1934 #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
1935 #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
1936 #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
1937 #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
1938 
1939 /*!
1940  * @}
1941  */ /* end of group GPIO_Register_Accessor_Macros */
1942 
1943 
1944 /*!
1945  * @}
1946  */ /* end of group GPIO_Peripheral_Access_Layer */
1947 
1948 
1949 /* ----------------------------------------------------------------------------
1950  -- I2C Peripheral Access Layer
1951  ---------------------------------------------------------------------------- */
1952 
1953 /*!
1954  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1955  * @{
1956  */
1957 
1958 /** I2C - Register Layout Typedef */
1959 typedef struct {
1960  __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
1961  __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
1962  __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
1963  __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
1964  __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
1965  __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
1966  __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
1967  __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
1968  __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
1969  __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
1970  __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
1971  __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
1972 } I2C_Type, *I2C_MemMapPtr;
1973 
1974 /* ----------------------------------------------------------------------------
1975  -- I2C - Register accessor macros
1976  ---------------------------------------------------------------------------- */
1977 
1978 /*!
1979  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
1980  * @{
1981  */
1982 
1983 
1984 /* I2C - Register accessors */
1985 #define I2C_A1_REG(base) ((base)->A1)
1986 #define I2C_F_REG(base) ((base)->F)
1987 #define I2C_C1_REG(base) ((base)->C1)
1988 #define I2C_S_REG(base) ((base)->S)
1989 #define I2C_D_REG(base) ((base)->D)
1990 #define I2C_C2_REG(base) ((base)->C2)
1991 #define I2C_FLT_REG(base) ((base)->FLT)
1992 #define I2C_RA_REG(base) ((base)->RA)
1993 #define I2C_SMB_REG(base) ((base)->SMB)
1994 #define I2C_A2_REG(base) ((base)->A2)
1995 #define I2C_SLTH_REG(base) ((base)->SLTH)
1996 #define I2C_SLTL_REG(base) ((base)->SLTL)
1997 
1998 /*!
1999  * @}
2000  */ /* end of group I2C_Register_Accessor_Macros */
2001 
2002 
2003 /* ----------------------------------------------------------------------------
2004  -- I2C Register Masks
2005  ---------------------------------------------------------------------------- */
2006 
2007 /*!
2008  * @addtogroup I2C_Register_Masks I2C Register Masks
2009  * @{
2010  */
2011 
2012 /* A1 Bit Fields */
2013 #define I2C_A1_AD_MASK 0xFEu
2014 #define I2C_A1_AD_SHIFT 1
2015 #define I2C_A1_AD_WIDTH 7
2016 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
2017 /* F Bit Fields */
2018 #define I2C_F_ICR_MASK 0x3Fu
2019 #define I2C_F_ICR_SHIFT 0
2020 #define I2C_F_ICR_WIDTH 6
2021 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
2022 #define I2C_F_MULT_MASK 0xC0u
2023 #define I2C_F_MULT_SHIFT 6
2024 #define I2C_F_MULT_WIDTH 2
2025 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
2026 /* C1 Bit Fields */
2027 #define I2C_C1_DMAEN_MASK 0x1u
2028 #define I2C_C1_DMAEN_SHIFT 0
2029 #define I2C_C1_DMAEN_WIDTH 1
2030 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
2031 #define I2C_C1_WUEN_MASK 0x2u
2032 #define I2C_C1_WUEN_SHIFT 1
2033 #define I2C_C1_WUEN_WIDTH 1
2034 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
2035 #define I2C_C1_RSTA_MASK 0x4u
2036 #define I2C_C1_RSTA_SHIFT 2
2037 #define I2C_C1_RSTA_WIDTH 1
2038 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
2039 #define I2C_C1_TXAK_MASK 0x8u
2040 #define I2C_C1_TXAK_SHIFT 3
2041 #define I2C_C1_TXAK_WIDTH 1
2042 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
2043 #define I2C_C1_TX_MASK 0x10u
2044 #define I2C_C1_TX_SHIFT 4
2045 #define I2C_C1_TX_WIDTH 1
2046 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
2047 #define I2C_C1_MST_MASK 0x20u
2048 #define I2C_C1_MST_SHIFT 5
2049 #define I2C_C1_MST_WIDTH 1
2050 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
2051 #define I2C_C1_IICIE_MASK 0x40u
2052 #define I2C_C1_IICIE_SHIFT 6
2053 #define I2C_C1_IICIE_WIDTH 1
2054 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
2055 #define I2C_C1_IICEN_MASK 0x80u
2056 #define I2C_C1_IICEN_SHIFT 7
2057 #define I2C_C1_IICEN_WIDTH 1
2058 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
2059 /* S Bit Fields */
2060 #define I2C_S_RXAK_MASK 0x1u
2061 #define I2C_S_RXAK_SHIFT 0
2062 #define I2C_S_RXAK_WIDTH 1
2063 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
2064 #define I2C_S_IICIF_MASK 0x2u
2065 #define I2C_S_IICIF_SHIFT 1
2066 #define I2C_S_IICIF_WIDTH 1
2067 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
2068 #define I2C_S_SRW_MASK 0x4u
2069 #define I2C_S_SRW_SHIFT 2
2070 #define I2C_S_SRW_WIDTH 1
2071 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
2072 #define I2C_S_RAM_MASK 0x8u
2073 #define I2C_S_RAM_SHIFT 3
2074 #define I2C_S_RAM_WIDTH 1
2075 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
2076 #define I2C_S_ARBL_MASK 0x10u
2077 #define I2C_S_ARBL_SHIFT 4
2078 #define I2C_S_ARBL_WIDTH 1
2079 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
2080 #define I2C_S_BUSY_MASK 0x20u
2081 #define I2C_S_BUSY_SHIFT 5
2082 #define I2C_S_BUSY_WIDTH 1
2083 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
2084 #define I2C_S_IAAS_MASK 0x40u
2085 #define I2C_S_IAAS_SHIFT 6
2086 #define I2C_S_IAAS_WIDTH 1
2087 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
2088 #define I2C_S_TCF_MASK 0x80u
2089 #define I2C_S_TCF_SHIFT 7
2090 #define I2C_S_TCF_WIDTH 1
2091 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
2092 /* D Bit Fields */
2093 #define I2C_D_DATA_MASK 0xFFu
2094 #define I2C_D_DATA_SHIFT 0
2095 #define I2C_D_DATA_WIDTH 8
2096 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
2097 /* C2 Bit Fields */
2098 #define I2C_C2_AD_MASK 0x7u
2099 #define I2C_C2_AD_SHIFT 0
2100 #define I2C_C2_AD_WIDTH 3
2101 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
2102 #define I2C_C2_RMEN_MASK 0x8u
2103 #define I2C_C2_RMEN_SHIFT 3
2104 #define I2C_C2_RMEN_WIDTH 1
2105 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
2106 #define I2C_C2_SBRC_MASK 0x10u
2107 #define I2C_C2_SBRC_SHIFT 4
2108 #define I2C_C2_SBRC_WIDTH 1
2109 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
2110 #define I2C_C2_HDRS_MASK 0x20u
2111 #define I2C_C2_HDRS_SHIFT 5
2112 #define I2C_C2_HDRS_WIDTH 1
2113 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
2114 #define I2C_C2_ADEXT_MASK 0x40u
2115 #define I2C_C2_ADEXT_SHIFT 6
2116 #define I2C_C2_ADEXT_WIDTH 1
2117 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
2118 #define I2C_C2_GCAEN_MASK 0x80u
2119 #define I2C_C2_GCAEN_SHIFT 7
2120 #define I2C_C2_GCAEN_WIDTH 1
2121 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
2122 /* FLT Bit Fields */
2123 #define I2C_FLT_FLT_MASK 0x1Fu
2124 #define I2C_FLT_FLT_SHIFT 0
2125 #define I2C_FLT_FLT_WIDTH 5
2126 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
2127 #define I2C_FLT_STOPIE_MASK 0x20u
2128 #define I2C_FLT_STOPIE_SHIFT 5
2129 #define I2C_FLT_STOPIE_WIDTH 1
2130 #define I2C_FLT_STOPIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPIE_SHIFT))&I2C_FLT_STOPIE_MASK)
2131 #define I2C_FLT_STOPF_MASK 0x40u
2132 #define I2C_FLT_STOPF_SHIFT 6
2133 #define I2C_FLT_STOPF_WIDTH 1
2134 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
2135 #define I2C_FLT_SHEN_MASK 0x80u
2136 #define I2C_FLT_SHEN_SHIFT 7
2137 #define I2C_FLT_SHEN_WIDTH 1
2138 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
2139 /* RA Bit Fields */
2140 #define I2C_RA_RAD_MASK 0xFEu
2141 #define I2C_RA_RAD_SHIFT 1
2142 #define I2C_RA_RAD_WIDTH 7
2143 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
2144 /* SMB Bit Fields */
2145 #define I2C_SMB_SHTF2IE_MASK 0x1u
2146 #define I2C_SMB_SHTF2IE_SHIFT 0
2147 #define I2C_SMB_SHTF2IE_WIDTH 1
2148 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
2149 #define I2C_SMB_SHTF2_MASK 0x2u
2150 #define I2C_SMB_SHTF2_SHIFT 1
2151 #define I2C_SMB_SHTF2_WIDTH 1
2152 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
2153 #define I2C_SMB_SHTF1_MASK 0x4u
2154 #define I2C_SMB_SHTF1_SHIFT 2
2155 #define I2C_SMB_SHTF1_WIDTH 1
2156 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
2157 #define I2C_SMB_SLTF_MASK 0x8u
2158 #define I2C_SMB_SLTF_SHIFT 3
2159 #define I2C_SMB_SLTF_WIDTH 1
2160 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
2161 #define I2C_SMB_TCKSEL_MASK 0x10u
2162 #define I2C_SMB_TCKSEL_SHIFT 4
2163 #define I2C_SMB_TCKSEL_WIDTH 1
2164 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
2165 #define I2C_SMB_SIICAEN_MASK 0x20u
2166 #define I2C_SMB_SIICAEN_SHIFT 5
2167 #define I2C_SMB_SIICAEN_WIDTH 1
2168 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
2169 #define I2C_SMB_ALERTEN_MASK 0x40u
2170 #define I2C_SMB_ALERTEN_SHIFT 6
2171 #define I2C_SMB_ALERTEN_WIDTH 1
2172 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
2173 #define I2C_SMB_FACK_MASK 0x80u
2174 #define I2C_SMB_FACK_SHIFT 7
2175 #define I2C_SMB_FACK_WIDTH 1
2176 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
2177 /* A2 Bit Fields */
2178 #define I2C_A2_SAD_MASK 0xFEu
2179 #define I2C_A2_SAD_SHIFT 1
2180 #define I2C_A2_SAD_WIDTH 7
2181 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
2182 /* SLTH Bit Fields */
2183 #define I2C_SLTH_SSLT_MASK 0xFFu
2184 #define I2C_SLTH_SSLT_SHIFT 0
2185 #define I2C_SLTH_SSLT_WIDTH 8
2186 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
2187 /* SLTL Bit Fields */
2188 #define I2C_SLTL_SSLT_MASK 0xFFu
2189 #define I2C_SLTL_SSLT_SHIFT 0
2190 #define I2C_SLTL_SSLT_WIDTH 8
2191 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
2192 
2193 /*!
2194  * @}
2195  */ /* end of group I2C_Register_Masks */
2196 
2197 
2198 /* I2C - Peripheral instance base addresses */
2199 /** Peripheral I2C0 base address */
2200 #define I2C0_BASE (0x40066000u)
2201 /** Peripheral I2C0 base pointer */
2202 #define I2C0 ((I2C_Type *)I2C0_BASE)
2203 #define I2C0_BASE_PTR (I2C0)
2204 /** Peripheral I2C1 base address */
2205 #define I2C1_BASE (0x40067000u)
2206 /** Peripheral I2C1 base pointer */
2207 #define I2C1 ((I2C_Type *)I2C1_BASE)
2208 #define I2C1_BASE_PTR (I2C1)
2209 /** Array initializer of I2C peripheral base addresses */
2210 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
2211 /** Array initializer of I2C peripheral base pointers */
2212 #define I2C_BASE_PTRS { I2C0, I2C1 }
2213 /** Interrupt vectors for the I2C peripheral type */
2214 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
2215 
2216 /* ----------------------------------------------------------------------------
2217  -- I2C - Register accessor macros
2218  ---------------------------------------------------------------------------- */
2219 
2220 /*!
2221  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
2222  * @{
2223  */
2224 
2225 
2226 /* I2C - Register instance definitions */
2227 /* I2C0 */
2228 #define I2C0_A1 I2C_A1_REG(I2C0)
2229 #define I2C0_F I2C_F_REG(I2C0)
2230 #define I2C0_C1 I2C_C1_REG(I2C0)
2231 #define I2C0_S I2C_S_REG(I2C0)
2232 #define I2C0_D I2C_D_REG(I2C0)
2233 #define I2C0_C2 I2C_C2_REG(I2C0)
2234 #define I2C0_FLT I2C_FLT_REG(I2C0)
2235 #define I2C0_RA I2C_RA_REG(I2C0)
2236 #define I2C0_SMB I2C_SMB_REG(I2C0)
2237 #define I2C0_A2 I2C_A2_REG(I2C0)
2238 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
2239 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
2240 /* I2C1 */
2241 #define I2C1_A1 I2C_A1_REG(I2C1)
2242 #define I2C1_F I2C_F_REG(I2C1)
2243 #define I2C1_C1 I2C_C1_REG(I2C1)
2244 #define I2C1_S I2C_S_REG(I2C1)
2245 #define I2C1_D I2C_D_REG(I2C1)
2246 #define I2C1_C2 I2C_C2_REG(I2C1)
2247 #define I2C1_FLT I2C_FLT_REG(I2C1)
2248 #define I2C1_RA I2C_RA_REG(I2C1)
2249 #define I2C1_SMB I2C_SMB_REG(I2C1)
2250 #define I2C1_A2 I2C_A2_REG(I2C1)
2251 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
2252 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
2253 
2254 /*!
2255  * @}
2256  */ /* end of group I2C_Register_Accessor_Macros */
2257 
2258 
2259 /*!
2260  * @}
2261  */ /* end of group I2C_Peripheral_Access_Layer */
2262 
2263 
2264 /* ----------------------------------------------------------------------------
2265  -- LLWU Peripheral Access Layer
2266  ---------------------------------------------------------------------------- */
2267 
2268 /*!
2269  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
2270  * @{
2271  */
2272 
2273 /** LLWU - Register Layout Typedef */
2274 typedef struct {
2275  __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
2276  __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
2277  __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
2278  __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
2279  __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
2280  __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
2281  __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
2282  __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
2283  __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
2284  __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
2285 } LLWU_Type, *LLWU_MemMapPtr;
2286 
2287 /* ----------------------------------------------------------------------------
2288  -- LLWU - Register accessor macros
2289  ---------------------------------------------------------------------------- */
2290 
2291 /*!
2292  * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
2293  * @{
2294  */
2295 
2296 
2297 /* LLWU - Register accessors */
2298 #define LLWU_PE1_REG(base) ((base)->PE1)
2299 #define LLWU_PE2_REG(base) ((base)->PE2)
2300 #define LLWU_PE3_REG(base) ((base)->PE3)
2301 #define LLWU_PE4_REG(base) ((base)->PE4)
2302 #define LLWU_ME_REG(base) ((base)->ME)
2303 #define LLWU_F1_REG(base) ((base)->F1)
2304 #define LLWU_F2_REG(base) ((base)->F2)
2305 #define LLWU_F3_REG(base) ((base)->F3)
2306 #define LLWU_FILT1_REG(base) ((base)->FILT1)
2307 #define LLWU_FILT2_REG(base) ((base)->FILT2)
2308 
2309 /*!
2310  * @}
2311  */ /* end of group LLWU_Register_Accessor_Macros */
2312 
2313 
2314 /* ----------------------------------------------------------------------------
2315  -- LLWU Register Masks
2316  ---------------------------------------------------------------------------- */
2317 
2318 /*!
2319  * @addtogroup LLWU_Register_Masks LLWU Register Masks
2320  * @{
2321  */
2322 
2323 /* PE1 Bit Fields */
2324 #define LLWU_PE1_WUPE0_MASK 0x3u
2325 #define LLWU_PE1_WUPE0_SHIFT 0
2326 #define LLWU_PE1_WUPE0_WIDTH 2
2327 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
2328 #define LLWU_PE1_WUPE1_MASK 0xCu
2329 #define LLWU_PE1_WUPE1_SHIFT 2
2330 #define LLWU_PE1_WUPE1_WIDTH 2
2331 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
2332 #define LLWU_PE1_WUPE2_MASK 0x30u
2333 #define LLWU_PE1_WUPE2_SHIFT 4
2334 #define LLWU_PE1_WUPE2_WIDTH 2
2335 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
2336 #define LLWU_PE1_WUPE3_MASK 0xC0u
2337 #define LLWU_PE1_WUPE3_SHIFT 6
2338 #define LLWU_PE1_WUPE3_WIDTH 2
2339 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
2340 /* PE2 Bit Fields */
2341 #define LLWU_PE2_WUPE4_MASK 0x3u
2342 #define LLWU_PE2_WUPE4_SHIFT 0
2343 #define LLWU_PE2_WUPE4_WIDTH 2
2344 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
2345 #define LLWU_PE2_WUPE5_MASK 0xCu
2346 #define LLWU_PE2_WUPE5_SHIFT 2
2347 #define LLWU_PE2_WUPE5_WIDTH 2
2348 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
2349 #define LLWU_PE2_WUPE6_MASK 0x30u
2350 #define LLWU_PE2_WUPE6_SHIFT 4
2351 #define LLWU_PE2_WUPE6_WIDTH 2
2352 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
2353 #define LLWU_PE2_WUPE7_MASK 0xC0u
2354 #define LLWU_PE2_WUPE7_SHIFT 6
2355 #define LLWU_PE2_WUPE7_WIDTH 2
2356 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
2357 /* PE3 Bit Fields */
2358 #define LLWU_PE3_WUPE8_MASK 0x3u
2359 #define LLWU_PE3_WUPE8_SHIFT 0
2360 #define LLWU_PE3_WUPE8_WIDTH 2
2361 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
2362 #define LLWU_PE3_WUPE9_MASK 0xCu
2363 #define LLWU_PE3_WUPE9_SHIFT 2
2364 #define LLWU_PE3_WUPE9_WIDTH 2
2365 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
2366 #define LLWU_PE3_WUPE10_MASK 0x30u
2367 #define LLWU_PE3_WUPE10_SHIFT 4
2368 #define LLWU_PE3_WUPE10_WIDTH 2
2369 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
2370 #define LLWU_PE3_WUPE11_MASK 0xC0u
2371 #define LLWU_PE3_WUPE11_SHIFT 6
2372 #define LLWU_PE3_WUPE11_WIDTH 2
2373 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
2374 /* PE4 Bit Fields */
2375 #define LLWU_PE4_WUPE12_MASK 0x3u
2376 #define LLWU_PE4_WUPE12_SHIFT 0
2377 #define LLWU_PE4_WUPE12_WIDTH 2
2378 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
2379 #define LLWU_PE4_WUPE13_MASK 0xCu
2380 #define LLWU_PE4_WUPE13_SHIFT 2
2381 #define LLWU_PE4_WUPE13_WIDTH 2
2382 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
2383 #define LLWU_PE4_WUPE14_MASK 0x30u
2384 #define LLWU_PE4_WUPE14_SHIFT 4
2385 #define LLWU_PE4_WUPE14_WIDTH 2
2386 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
2387 #define LLWU_PE4_WUPE15_MASK 0xC0u
2388 #define LLWU_PE4_WUPE15_SHIFT 6
2389 #define LLWU_PE4_WUPE15_WIDTH 2
2390 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
2391 /* ME Bit Fields */
2392 #define LLWU_ME_WUME0_MASK 0x1u
2393 #define LLWU_ME_WUME0_SHIFT 0
2394 #define LLWU_ME_WUME0_WIDTH 1
2395 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
2396 #define LLWU_ME_WUME1_MASK 0x2u
2397 #define LLWU_ME_WUME1_SHIFT 1
2398 #define LLWU_ME_WUME1_WIDTH 1
2399 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
2400 #define LLWU_ME_WUME2_MASK 0x4u
2401 #define LLWU_ME_WUME2_SHIFT 2
2402 #define LLWU_ME_WUME2_WIDTH 1
2403 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
2404 #define LLWU_ME_WUME3_MASK 0x8u
2405 #define LLWU_ME_WUME3_SHIFT 3
2406 #define LLWU_ME_WUME3_WIDTH 1
2407 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
2408 #define LLWU_ME_WUME4_MASK 0x10u
2409 #define LLWU_ME_WUME4_SHIFT 4
2410 #define LLWU_ME_WUME4_WIDTH 1
2411 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
2412 #define LLWU_ME_WUME5_MASK 0x20u
2413 #define LLWU_ME_WUME5_SHIFT 5
2414 #define LLWU_ME_WUME5_WIDTH 1
2415 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
2416 #define LLWU_ME_WUME6_MASK 0x40u
2417 #define LLWU_ME_WUME6_SHIFT 6
2418 #define LLWU_ME_WUME6_WIDTH 1
2419 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
2420 #define LLWU_ME_WUME7_MASK 0x80u
2421 #define LLWU_ME_WUME7_SHIFT 7
2422 #define LLWU_ME_WUME7_WIDTH 1
2423 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
2424 /* F1 Bit Fields */
2425 #define LLWU_F1_WUF0_MASK 0x1u
2426 #define LLWU_F1_WUF0_SHIFT 0
2427 #define LLWU_F1_WUF0_WIDTH 1
2428 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
2429 #define LLWU_F1_WUF1_MASK 0x2u
2430 #define LLWU_F1_WUF1_SHIFT 1
2431 #define LLWU_F1_WUF1_WIDTH 1
2432 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
2433 #define LLWU_F1_WUF2_MASK 0x4u
2434 #define LLWU_F1_WUF2_SHIFT 2
2435 #define LLWU_F1_WUF2_WIDTH 1
2436 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
2437 #define LLWU_F1_WUF3_MASK 0x8u
2438 #define LLWU_F1_WUF3_SHIFT 3
2439 #define LLWU_F1_WUF3_WIDTH 1
2440 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
2441 #define LLWU_F1_WUF4_MASK 0x10u
2442 #define LLWU_F1_WUF4_SHIFT 4
2443 #define LLWU_F1_WUF4_WIDTH 1
2444 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
2445 #define LLWU_F1_WUF5_MASK 0x20u
2446 #define LLWU_F1_WUF5_SHIFT 5
2447 #define LLWU_F1_WUF5_WIDTH 1
2448 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
2449 #define LLWU_F1_WUF6_MASK 0x40u
2450 #define LLWU_F1_WUF6_SHIFT 6
2451 #define LLWU_F1_WUF6_WIDTH 1
2452 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
2453 #define LLWU_F1_WUF7_MASK 0x80u
2454 #define LLWU_F1_WUF7_SHIFT 7
2455 #define LLWU_F1_WUF7_WIDTH 1
2456 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
2457 /* F2 Bit Fields */
2458 #define LLWU_F2_WUF8_MASK 0x1u
2459 #define LLWU_F2_WUF8_SHIFT 0
2460 #define LLWU_F2_WUF8_WIDTH 1
2461 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
2462 #define LLWU_F2_WUF9_MASK 0x2u
2463 #define LLWU_F2_WUF9_SHIFT 1
2464 #define LLWU_F2_WUF9_WIDTH 1
2465 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
2466 #define LLWU_F2_WUF10_MASK 0x4u
2467 #define LLWU_F2_WUF10_SHIFT 2
2468 #define LLWU_F2_WUF10_WIDTH 1
2469 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
2470 #define LLWU_F2_WUF11_MASK 0x8u
2471 #define LLWU_F2_WUF11_SHIFT 3
2472 #define LLWU_F2_WUF11_WIDTH 1
2473 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
2474 #define LLWU_F2_WUF12_MASK 0x10u
2475 #define LLWU_F2_WUF12_SHIFT 4
2476 #define LLWU_F2_WUF12_WIDTH 1
2477 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
2478 #define LLWU_F2_WUF13_MASK 0x20u
2479 #define LLWU_F2_WUF13_SHIFT 5
2480 #define LLWU_F2_WUF13_WIDTH 1
2481 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
2482 #define LLWU_F2_WUF14_MASK 0x40u
2483 #define LLWU_F2_WUF14_SHIFT 6
2484 #define LLWU_F2_WUF14_WIDTH 1
2485 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
2486 #define LLWU_F2_WUF15_MASK 0x80u
2487 #define LLWU_F2_WUF15_SHIFT 7
2488 #define LLWU_F2_WUF15_WIDTH 1
2489 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
2490 /* F3 Bit Fields */
2491 #define LLWU_F3_MWUF0_MASK 0x1u
2492 #define LLWU_F3_MWUF0_SHIFT 0
2493 #define LLWU_F3_MWUF0_WIDTH 1
2494 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
2495 #define LLWU_F3_MWUF1_MASK 0x2u
2496 #define LLWU_F3_MWUF1_SHIFT 1
2497 #define LLWU_F3_MWUF1_WIDTH 1
2498 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
2499 #define LLWU_F3_MWUF2_MASK 0x4u
2500 #define LLWU_F3_MWUF2_SHIFT 2
2501 #define LLWU_F3_MWUF2_WIDTH 1
2502 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
2503 #define LLWU_F3_MWUF3_MASK 0x8u
2504 #define LLWU_F3_MWUF3_SHIFT 3
2505 #define LLWU_F3_MWUF3_WIDTH 1
2506 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
2507 #define LLWU_F3_MWUF4_MASK 0x10u
2508 #define LLWU_F3_MWUF4_SHIFT 4
2509 #define LLWU_F3_MWUF4_WIDTH 1
2510 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
2511 #define LLWU_F3_MWUF5_MASK 0x20u
2512 #define LLWU_F3_MWUF5_SHIFT 5
2513 #define LLWU_F3_MWUF5_WIDTH 1
2514 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
2515 #define LLWU_F3_MWUF6_MASK 0x40u
2516 #define LLWU_F3_MWUF6_SHIFT 6
2517 #define LLWU_F3_MWUF6_WIDTH 1
2518 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
2519 #define LLWU_F3_MWUF7_MASK 0x80u
2520 #define LLWU_F3_MWUF7_SHIFT 7
2521 #define LLWU_F3_MWUF7_WIDTH 1
2522 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
2523 /* FILT1 Bit Fields */
2524 #define LLWU_FILT1_FILTSEL_MASK 0xFu
2525 #define LLWU_FILT1_FILTSEL_SHIFT 0
2526 #define LLWU_FILT1_FILTSEL_WIDTH 4
2527 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
2528 #define LLWU_FILT1_FILTE_MASK 0x60u
2529 #define LLWU_FILT1_FILTE_SHIFT 5
2530 #define LLWU_FILT1_FILTE_WIDTH 2
2531 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
2532 #define LLWU_FILT1_FILTF_MASK 0x80u
2533 #define LLWU_FILT1_FILTF_SHIFT 7
2534 #define LLWU_FILT1_FILTF_WIDTH 1
2535 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
2536 /* FILT2 Bit Fields */
2537 #define LLWU_FILT2_FILTSEL_MASK 0xFu
2538 #define LLWU_FILT2_FILTSEL_SHIFT 0
2539 #define LLWU_FILT2_FILTSEL_WIDTH 4
2540 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
2541 #define LLWU_FILT2_FILTE_MASK 0x60u
2542 #define LLWU_FILT2_FILTE_SHIFT 5
2543 #define LLWU_FILT2_FILTE_WIDTH 2
2544 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
2545 #define LLWU_FILT2_FILTF_MASK 0x80u
2546 #define LLWU_FILT2_FILTF_SHIFT 7
2547 #define LLWU_FILT2_FILTF_WIDTH 1
2548 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
2549 
2550 /*!
2551  * @}
2552  */ /* end of group LLWU_Register_Masks */
2553 
2554 
2555 /* LLWU - Peripheral instance base addresses */
2556 /** Peripheral LLWU base address */
2557 #define LLWU_BASE (0x4007C000u)
2558 /** Peripheral LLWU base pointer */
2559 #define LLWU ((LLWU_Type *)LLWU_BASE)
2560 #define LLWU_BASE_PTR (LLWU)
2561 /** Array initializer of LLWU peripheral base addresses */
2562 #define LLWU_BASE_ADDRS { LLWU_BASE }
2563 /** Array initializer of LLWU peripheral base pointers */
2564 #define LLWU_BASE_PTRS { LLWU }
2565 /** Interrupt vectors for the LLWU peripheral type */
2566 #define LLWU_IRQS { LLWU_IRQn }
2567 
2568 /* ----------------------------------------------------------------------------
2569  -- LLWU - Register accessor macros
2570  ---------------------------------------------------------------------------- */
2571 
2572 /*!
2573  * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
2574  * @{
2575  */
2576 
2577 
2578 /* LLWU - Register instance definitions */
2579 /* LLWU */
2580 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
2581 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
2582 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
2583 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
2584 #define LLWU_ME LLWU_ME_REG(LLWU)
2585 #define LLWU_F1 LLWU_F1_REG(LLWU)
2586 #define LLWU_F2 LLWU_F2_REG(LLWU)
2587 #define LLWU_F3 LLWU_F3_REG(LLWU)
2588 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
2589 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
2590 
2591 /*!
2592  * @}
2593  */ /* end of group LLWU_Register_Accessor_Macros */
2594 
2595 
2596 /*!
2597  * @}
2598  */ /* end of group LLWU_Peripheral_Access_Layer */
2599 
2600 
2601 /* ----------------------------------------------------------------------------
2602  -- LPTMR Peripheral Access Layer
2603  ---------------------------------------------------------------------------- */
2604 
2605 /*!
2606  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
2607  * @{
2608  */
2609 
2610 /** LPTMR - Register Layout Typedef */
2611 typedef struct {
2612  __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
2613  __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
2614  __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
2615  __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
2616 } LPTMR_Type, *LPTMR_MemMapPtr;
2617 
2618 /* ----------------------------------------------------------------------------
2619  -- LPTMR - Register accessor macros
2620  ---------------------------------------------------------------------------- */
2621 
2622 /*!
2623  * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
2624  * @{
2625  */
2626 
2627 
2628 /* LPTMR - Register accessors */
2629 #define LPTMR_CSR_REG(base) ((base)->CSR)
2630 #define LPTMR_PSR_REG(base) ((base)->PSR)
2631 #define LPTMR_CMR_REG(base) ((base)->CMR)
2632 #define LPTMR_CNR_REG(base) ((base)->CNR)
2633 
2634 /*!
2635  * @}
2636  */ /* end of group LPTMR_Register_Accessor_Macros */
2637 
2638 
2639 /* ----------------------------------------------------------------------------
2640  -- LPTMR Register Masks
2641  ---------------------------------------------------------------------------- */
2642 
2643 /*!
2644  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
2645  * @{
2646  */
2647 
2648 /* CSR Bit Fields */
2649 #define LPTMR_CSR_TEN_MASK 0x1u
2650 #define LPTMR_CSR_TEN_SHIFT 0
2651 #define LPTMR_CSR_TEN_WIDTH 1
2652 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
2653 #define LPTMR_CSR_TMS_MASK 0x2u
2654 #define LPTMR_CSR_TMS_SHIFT 1
2655 #define LPTMR_CSR_TMS_WIDTH 1
2656 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
2657 #define LPTMR_CSR_TFC_MASK 0x4u
2658 #define LPTMR_CSR_TFC_SHIFT 2
2659 #define LPTMR_CSR_TFC_WIDTH 1
2660 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
2661 #define LPTMR_CSR_TPP_MASK 0x8u
2662 #define LPTMR_CSR_TPP_SHIFT 3
2663 #define LPTMR_CSR_TPP_WIDTH 1
2664 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
2665 #define LPTMR_CSR_TPS_MASK 0x30u
2666 #define LPTMR_CSR_TPS_SHIFT 4
2667 #define LPTMR_CSR_TPS_WIDTH 2
2668 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
2669 #define LPTMR_CSR_TIE_MASK 0x40u
2670 #define LPTMR_CSR_TIE_SHIFT 6
2671 #define LPTMR_CSR_TIE_WIDTH 1
2672 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
2673 #define LPTMR_CSR_TCF_MASK 0x80u
2674 #define LPTMR_CSR_TCF_SHIFT 7
2675 #define LPTMR_CSR_TCF_WIDTH 1
2676 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
2677 /* PSR Bit Fields */
2678 #define LPTMR_PSR_PCS_MASK 0x3u
2679 #define LPTMR_PSR_PCS_SHIFT 0
2680 #define LPTMR_PSR_PCS_WIDTH 2
2681 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
2682 #define LPTMR_PSR_PBYP_MASK 0x4u
2683 #define LPTMR_PSR_PBYP_SHIFT 2
2684 #define LPTMR_PSR_PBYP_WIDTH 1
2685 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
2686 #define LPTMR_PSR_PRESCALE_MASK 0x78u
2687 #define LPTMR_PSR_PRESCALE_SHIFT 3
2688 #define LPTMR_PSR_PRESCALE_WIDTH 4
2689 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
2690 /* CMR Bit Fields */
2691 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
2692 #define LPTMR_CMR_COMPARE_SHIFT 0
2693 #define LPTMR_CMR_COMPARE_WIDTH 16
2694 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
2695 /* CNR Bit Fields */
2696 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
2697 #define LPTMR_CNR_COUNTER_SHIFT 0
2698 #define LPTMR_CNR_COUNTER_WIDTH 16
2699 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
2700 
2701 /*!
2702  * @}
2703  */ /* end of group LPTMR_Register_Masks */
2704 
2705 
2706 /* LPTMR - Peripheral instance base addresses */
2707 /** Peripheral LPTMR0 base address */
2708 #define LPTMR0_BASE (0x40040000u)
2709 /** Peripheral LPTMR0 base pointer */
2710 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
2711 #define LPTMR0_BASE_PTR (LPTMR0)
2712 /** Array initializer of LPTMR peripheral base addresses */
2713 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
2714 /** Array initializer of LPTMR peripheral base pointers */
2715 #define LPTMR_BASE_PTRS { LPTMR0 }
2716 /** Interrupt vectors for the LPTMR peripheral type */
2717 #define LPTMR_IRQS { LPTMR0_IRQn }
2718 
2719 /* ----------------------------------------------------------------------------
2720  -- LPTMR - Register accessor macros
2721  ---------------------------------------------------------------------------- */
2722 
2723 /*!
2724  * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
2725  * @{
2726  */
2727 
2728 
2729 /* LPTMR - Register instance definitions */
2730 /* LPTMR0 */
2731 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
2732 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
2733 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
2734 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
2735 
2736 /*!
2737  * @}
2738  */ /* end of group LPTMR_Register_Accessor_Macros */
2739 
2740 
2741 /*!
2742  * @}
2743  */ /* end of group LPTMR_Peripheral_Access_Layer */
2744 
2745 
2746 /* ----------------------------------------------------------------------------
2747  -- MCG Peripheral Access Layer
2748  ---------------------------------------------------------------------------- */
2749 
2750 /*!
2751  * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
2752  * @{
2753  */
2754 
2755 /** MCG - Register Layout Typedef */
2756 typedef struct {
2757  __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
2758  __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
2759  __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
2760  __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
2761  __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
2762  __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
2763  __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
2764  uint8_t RESERVED_0[1];
2765  __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
2766  uint8_t RESERVED_1[1];
2767  __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
2768  __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
2769  __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
2770  __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
2771  __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
2772  __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
2773 } MCG_Type, *MCG_MemMapPtr;
2774 
2775 /* ----------------------------------------------------------------------------
2776  -- MCG - Register accessor macros
2777  ---------------------------------------------------------------------------- */
2778 
2779 /*!
2780  * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
2781  * @{
2782  */
2783 
2784 
2785 /* MCG - Register accessors */
2786 #define MCG_C1_REG(base) ((base)->C1)
2787 #define MCG_C2_REG(base) ((base)->C2)
2788 #define MCG_C3_REG(base) ((base)->C3)
2789 #define MCG_C4_REG(base) ((base)->C4)
2790 #define MCG_C5_REG(base) ((base)->C5)
2791 #define MCG_C6_REG(base) ((base)->C6)
2792 #define MCG_S_REG(base) ((base)->S)
2793 #define MCG_SC_REG(base) ((base)->SC)
2794 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
2795 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
2796 #define MCG_C7_REG(base) ((base)->C7)
2797 #define MCG_C8_REG(base) ((base)->C8)
2798 #define MCG_C9_REG(base) ((base)->C9)
2799 #define MCG_C10_REG(base) ((base)->C10)
2800 
2801 /*!
2802  * @}
2803  */ /* end of group MCG_Register_Accessor_Macros */
2804 
2805 
2806 /* ----------------------------------------------------------------------------
2807  -- MCG Register Masks
2808  ---------------------------------------------------------------------------- */
2809 
2810 /*!
2811  * @addtogroup MCG_Register_Masks MCG Register Masks
2812  * @{
2813  */
2814 
2815 /* C1 Bit Fields */
2816 #define MCG_C1_IREFSTEN_MASK 0x1u
2817 #define MCG_C1_IREFSTEN_SHIFT 0
2818 #define MCG_C1_IREFSTEN_WIDTH 1
2819 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
2820 #define MCG_C1_IRCLKEN_MASK 0x2u
2821 #define MCG_C1_IRCLKEN_SHIFT 1
2822 #define MCG_C1_IRCLKEN_WIDTH 1
2823 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
2824 #define MCG_C1_IREFS_MASK 0x4u
2825 #define MCG_C1_IREFS_SHIFT 2
2826 #define MCG_C1_IREFS_WIDTH 1
2827 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
2828 #define MCG_C1_FRDIV_MASK 0x38u
2829 #define MCG_C1_FRDIV_SHIFT 3
2830 #define MCG_C1_FRDIV_WIDTH 3
2831 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
2832 #define MCG_C1_CLKS_MASK 0xC0u
2833 #define MCG_C1_CLKS_SHIFT 6
2834 #define MCG_C1_CLKS_WIDTH 2
2835 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
2836 /* C2 Bit Fields */
2837 #define MCG_C2_IRCS_MASK 0x1u
2838 #define MCG_C2_IRCS_SHIFT 0
2839 #define MCG_C2_IRCS_WIDTH 1
2840 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
2841 #define MCG_C2_LP_MASK 0x2u
2842 #define MCG_C2_LP_SHIFT 1
2843 #define MCG_C2_LP_WIDTH 1
2844 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
2845 #define MCG_C2_EREFS0_MASK 0x4u
2846 #define MCG_C2_EREFS0_SHIFT 2
2847 #define MCG_C2_EREFS0_WIDTH 1
2848 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS0_SHIFT))&MCG_C2_EREFS0_MASK)
2849 #define MCG_C2_HGO0_MASK 0x8u
2850 #define MCG_C2_HGO0_SHIFT 3
2851 #define MCG_C2_HGO0_WIDTH 1
2852 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO0_SHIFT))&MCG_C2_HGO0_MASK)
2853 #define MCG_C2_RANGE0_MASK 0x30u
2854 #define MCG_C2_RANGE0_SHIFT 4
2855 #define MCG_C2_RANGE0_WIDTH 2
2856 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
2857 #define MCG_C2_LOCRE0_MASK 0x80u
2858 #define MCG_C2_LOCRE0_SHIFT 7
2859 #define MCG_C2_LOCRE0_WIDTH 1
2860 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
2861 /* C3 Bit Fields */
2862 #define MCG_C3_SCTRIM_MASK 0xFFu
2863 #define MCG_C3_SCTRIM_SHIFT 0
2864 #define MCG_C3_SCTRIM_WIDTH 8
2865 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
2866 /* C4 Bit Fields */
2867 #define MCG_C4_SCFTRIM_MASK 0x1u
2868 #define MCG_C4_SCFTRIM_SHIFT 0
2869 #define MCG_C4_SCFTRIM_WIDTH 1
2870 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
2871 #define MCG_C4_FCTRIM_MASK 0x1Eu
2872 #define MCG_C4_FCTRIM_SHIFT 1
2873 #define MCG_C4_FCTRIM_WIDTH 4
2874 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
2875 #define MCG_C4_DRST_DRS_MASK 0x60u
2876 #define MCG_C4_DRST_DRS_SHIFT 5
2877 #define MCG_C4_DRST_DRS_WIDTH 2
2878 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
2879 #define MCG_C4_DMX32_MASK 0x80u
2880 #define MCG_C4_DMX32_SHIFT 7
2881 #define MCG_C4_DMX32_WIDTH 1
2882 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
2883 /* C5 Bit Fields */
2884 #define MCG_C5_PRDIV0_MASK 0x1Fu
2885 #define MCG_C5_PRDIV0_SHIFT 0
2886 #define MCG_C5_PRDIV0_WIDTH 5
2887 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
2888 #define MCG_C5_PLLSTEN0_MASK 0x20u
2889 #define MCG_C5_PLLSTEN0_SHIFT 5
2890 #define MCG_C5_PLLSTEN0_WIDTH 1
2891 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
2892 #define MCG_C5_PLLCLKEN0_MASK 0x40u
2893 #define MCG_C5_PLLCLKEN0_SHIFT 6
2894 #define MCG_C5_PLLCLKEN0_WIDTH 1
2895 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
2896 /* C6 Bit Fields */
2897 #define MCG_C6_VDIV0_MASK 0x1Fu
2898 #define MCG_C6_VDIV0_SHIFT 0
2899 #define MCG_C6_VDIV0_WIDTH 5
2900 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
2901 #define MCG_C6_CME0_MASK 0x20u
2902 #define MCG_C6_CME0_SHIFT 5
2903 #define MCG_C6_CME0_WIDTH 1
2904 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
2905 #define MCG_C6_PLLS_MASK 0x40u
2906 #define MCG_C6_PLLS_SHIFT 6
2907 #define MCG_C6_PLLS_WIDTH 1
2908 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
2909 #define MCG_C6_LOLIE0_MASK 0x80u
2910 #define MCG_C6_LOLIE0_SHIFT 7
2911 #define MCG_C6_LOLIE0_WIDTH 1
2912 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
2913 /* S Bit Fields */
2914 #define MCG_S_IRCST_MASK 0x1u
2915 #define MCG_S_IRCST_SHIFT 0
2916 #define MCG_S_IRCST_WIDTH 1
2917 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
2918 #define MCG_S_OSCINIT0_MASK 0x2u
2919 #define MCG_S_OSCINIT0_SHIFT 1
2920 #define MCG_S_OSCINIT0_WIDTH 1
2921 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
2922 #define MCG_S_CLKST_MASK 0xCu
2923 #define MCG_S_CLKST_SHIFT 2
2924 #define MCG_S_CLKST_WIDTH 2
2925 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
2926 #define MCG_S_IREFST_MASK 0x10u
2927 #define MCG_S_IREFST_SHIFT 4
2928 #define MCG_S_IREFST_WIDTH 1
2929 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
2930 #define MCG_S_PLLST_MASK 0x20u
2931 #define MCG_S_PLLST_SHIFT 5
2932 #define MCG_S_PLLST_WIDTH 1
2933 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
2934 #define MCG_S_LOCK0_MASK 0x40u
2935 #define MCG_S_LOCK0_SHIFT 6
2936 #define MCG_S_LOCK0_WIDTH 1
2937 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
2938 #define MCG_S_LOLS0_MASK 0x80u
2939 #define MCG_S_LOLS0_SHIFT 7
2940 #define MCG_S_LOLS0_WIDTH 1
2941 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
2942 /* SC Bit Fields */
2943 #define MCG_SC_LOCS0_MASK 0x1u
2944 #define MCG_SC_LOCS0_SHIFT 0
2945 #define MCG_SC_LOCS0_WIDTH 1
2946 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
2947 #define MCG_SC_FCRDIV_MASK 0xEu
2948 #define MCG_SC_FCRDIV_SHIFT 1
2949 #define MCG_SC_FCRDIV_WIDTH 3
2950 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
2951 #define MCG_SC_FLTPRSRV_MASK 0x10u
2952 #define MCG_SC_FLTPRSRV_SHIFT 4
2953 #define MCG_SC_FLTPRSRV_WIDTH 1
2954 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
2955 #define MCG_SC_ATMF_MASK 0x20u
2956 #define MCG_SC_ATMF_SHIFT 5
2957 #define MCG_SC_ATMF_WIDTH 1
2958 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
2959 #define MCG_SC_ATMS_MASK 0x40u
2960 #define MCG_SC_ATMS_SHIFT 6
2961 #define MCG_SC_ATMS_WIDTH 1
2962 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
2963 #define MCG_SC_ATME_MASK 0x80u
2964 #define MCG_SC_ATME_SHIFT 7
2965 #define MCG_SC_ATME_WIDTH 1
2966 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
2967 /* ATCVH Bit Fields */
2968 #define MCG_ATCVH_ATCVH_MASK 0xFFu
2969 #define MCG_ATCVH_ATCVH_SHIFT 0
2970 #define MCG_ATCVH_ATCVH_WIDTH 8
2971 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
2972 /* ATCVL Bit Fields */
2973 #define MCG_ATCVL_ATCVL_MASK 0xFFu
2974 #define MCG_ATCVL_ATCVL_SHIFT 0
2975 #define MCG_ATCVL_ATCVL_WIDTH 8
2976 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
2977 /* C8 Bit Fields */
2978 #define MCG_C8_LOLRE_MASK 0x40u
2979 #define MCG_C8_LOLRE_SHIFT 6
2980 #define MCG_C8_LOLRE_WIDTH 1
2981 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
2982 
2983 /*!
2984  * @}
2985  */ /* end of group MCG_Register_Masks */
2986 
2987 
2988 /* MCG - Peripheral instance base addresses */
2989 /** Peripheral MCG base address */
2990 #define MCG_BASE (0x40064000u)
2991 /** Peripheral MCG base pointer */
2992 #define MCG ((MCG_Type *)MCG_BASE)
2993 #define MCG_BASE_PTR (MCG)
2994 /** Array initializer of MCG peripheral base addresses */
2995 #define MCG_BASE_ADDRS { MCG_BASE }
2996 /** Array initializer of MCG peripheral base pointers */
2997 #define MCG_BASE_PTRS { MCG }
2998 /** Interrupt vectors for the MCG peripheral type */
2999 #define MCG_IRQS { MCG_IRQn }
3000 
3001 /* ----------------------------------------------------------------------------
3002  -- MCG - Register accessor macros
3003  ---------------------------------------------------------------------------- */
3004 
3005 /*!
3006  * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
3007  * @{
3008  */
3009 
3010 
3011 /* MCG - Register instance definitions */
3012 /* MCG */
3013 #define MCG_C1 MCG_C1_REG(MCG)
3014 #define MCG_C2 MCG_C2_REG(MCG)
3015 #define MCG_C3 MCG_C3_REG(MCG)
3016 #define MCG_C4 MCG_C4_REG(MCG)
3017 #define MCG_C5 MCG_C5_REG(MCG)
3018 #define MCG_C6 MCG_C6_REG(MCG)
3019 #define MCG_S MCG_S_REG(MCG)
3020 #define MCG_SC MCG_SC_REG(MCG)
3021 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
3022 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
3023 #define MCG_C7 MCG_C7_REG(MCG)
3024 #define MCG_C8 MCG_C8_REG(MCG)
3025 #define MCG_C9 MCG_C9_REG(MCG)
3026 #define MCG_C10 MCG_C10_REG(MCG)
3027 
3028 /*!
3029  * @}
3030  */ /* end of group MCG_Register_Accessor_Macros */
3031 
3032 /* MCG C2[EREFS] backward compatibility */
3033 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
3034 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
3035 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
3036 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
3037 
3038 /* MCG C2[HGO] backward compatibility */
3039 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
3040 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
3041 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
3042 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
3043 
3044 /* MCG C2[RANGE] backward compatibility */
3045 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
3046 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
3047 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
3048 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
3049 
3050 
3051 /*!
3052  * @}
3053  */ /* end of group MCG_Peripheral_Access_Layer */
3054 
3055 
3056 /* ----------------------------------------------------------------------------
3057  -- MCM Peripheral Access Layer
3058  ---------------------------------------------------------------------------- */
3059 
3060 /*!
3061  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
3062  * @{
3063  */
3064 
3065 /** MCM - Register Layout Typedef */
3066 typedef struct {
3067  uint8_t RESERVED_0[8];
3068  __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
3069  __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
3070  __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
3071  uint8_t RESERVED_1[48];
3072  __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
3073 } MCM_Type, *MCM_MemMapPtr;
3074 
3075 /* ----------------------------------------------------------------------------
3076  -- MCM - Register accessor macros
3077  ---------------------------------------------------------------------------- */
3078 
3079 /*!
3080  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
3081  * @{
3082  */
3083 
3084 
3085 /* MCM - Register accessors */
3086 #define MCM_PLASC_REG(base) ((base)->PLASC)
3087 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
3088 #define MCM_PLACR_REG(base) ((base)->PLACR)
3089 #define MCM_CPO_REG(base) ((base)->CPO)
3090 
3091 /*!
3092  * @}
3093  */ /* end of group MCM_Register_Accessor_Macros */
3094 
3095 
3096 /* ----------------------------------------------------------------------------
3097  -- MCM Register Masks
3098  ---------------------------------------------------------------------------- */
3099 
3100 /*!
3101  * @addtogroup MCM_Register_Masks MCM Register Masks
3102  * @{
3103  */
3104 
3105 /* PLASC Bit Fields */
3106 #define MCM_PLASC_ASC_MASK 0xFFu
3107 #define MCM_PLASC_ASC_SHIFT 0
3108 #define MCM_PLASC_ASC_WIDTH 8
3109 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
3110 /* PLAMC Bit Fields */
3111 #define MCM_PLAMC_AMC_MASK 0xFFu
3112 #define MCM_PLAMC_AMC_SHIFT 0
3113 #define MCM_PLAMC_AMC_WIDTH 8
3114 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
3115 /* PLACR Bit Fields */
3116 #define MCM_PLACR_ARB_MASK 0x200u
3117 #define MCM_PLACR_ARB_SHIFT 9
3118 #define MCM_PLACR_ARB_WIDTH 1
3119 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
3120 #define MCM_PLACR_CFCC_MASK 0x400u
3121 #define MCM_PLACR_CFCC_SHIFT 10
3122 #define MCM_PLACR_CFCC_WIDTH 1
3123 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_CFCC_SHIFT))&MCM_PLACR_CFCC_MASK)
3124 #define MCM_PLACR_DFCDA_MASK 0x800u
3125 #define MCM_PLACR_DFCDA_SHIFT 11
3126 #define MCM_PLACR_DFCDA_WIDTH 1
3127 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCDA_SHIFT))&MCM_PLACR_DFCDA_MASK)
3128 #define MCM_PLACR_DFCIC_MASK 0x1000u
3129 #define MCM_PLACR_DFCIC_SHIFT 12
3130 #define MCM_PLACR_DFCIC_WIDTH 1
3131 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCIC_SHIFT))&MCM_PLACR_DFCIC_MASK)
3132 #define MCM_PLACR_DFCC_MASK 0x2000u
3133 #define MCM_PLACR_DFCC_SHIFT 13
3134 #define MCM_PLACR_DFCC_WIDTH 1
3135 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCC_SHIFT))&MCM_PLACR_DFCC_MASK)
3136 #define MCM_PLACR_EFDS_MASK 0x4000u
3137 #define MCM_PLACR_EFDS_SHIFT 14
3138 #define MCM_PLACR_EFDS_WIDTH 1
3139 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)
3140 #define MCM_PLACR_DFCS_MASK 0x8000u
3141 #define MCM_PLACR_DFCS_SHIFT 15
3142 #define MCM_PLACR_DFCS_WIDTH 1
3143 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_DFCS_SHIFT))&MCM_PLACR_DFCS_MASK)
3144 #define MCM_PLACR_ESFC_MASK 0x10000u
3145 #define MCM_PLACR_ESFC_SHIFT 16
3146 #define MCM_PLACR_ESFC_WIDTH 1
3147 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ESFC_SHIFT))&MCM_PLACR_ESFC_MASK)
3148 /* CPO Bit Fields */
3149 #define MCM_CPO_CPOREQ_MASK 0x1u
3150 #define MCM_CPO_CPOREQ_SHIFT 0
3151 #define MCM_CPO_CPOREQ_WIDTH 1
3152 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
3153 #define MCM_CPO_CPOACK_MASK 0x2u
3154 #define MCM_CPO_CPOACK_SHIFT 1
3155 #define MCM_CPO_CPOACK_WIDTH 1
3156 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
3157 #define MCM_CPO_CPOWOI_MASK 0x4u
3158 #define MCM_CPO_CPOWOI_SHIFT 2
3159 #define MCM_CPO_CPOWOI_WIDTH 1
3160 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
3161 
3162 /*!
3163  * @}
3164  */ /* end of group MCM_Register_Masks */
3165 
3166 
3167 /* MCM - Peripheral instance base addresses */
3168 /** Peripheral MCM base address */
3169 #define MCM_BASE (0xF0003000u)
3170 /** Peripheral MCM base pointer */
3171 #define MCM ((MCM_Type *)MCM_BASE)
3172 #define MCM_BASE_PTR (MCM)
3173 /** Array initializer of MCM peripheral base addresses */
3174 #define MCM_BASE_ADDRS { MCM_BASE }
3175 /** Array initializer of MCM peripheral base pointers */
3176 #define MCM_BASE_PTRS { MCM }
3177 
3178 /* ----------------------------------------------------------------------------
3179  -- MCM - Register accessor macros
3180  ---------------------------------------------------------------------------- */
3181 
3182 /*!
3183  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
3184  * @{
3185  */
3186 
3187 
3188 /* MCM - Register instance definitions */
3189 /* MCM */
3190 #define MCM_PLASC MCM_PLASC_REG(MCM)
3191 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
3192 #define MCM_PLACR MCM_PLACR_REG(MCM)
3193 #define MCM_CPO MCM_CPO_REG(MCM)
3194 
3195 /*!
3196  * @}
3197  */ /* end of group MCM_Register_Accessor_Macros */
3198 
3199 
3200 /*!
3201  * @}
3202  */ /* end of group MCM_Peripheral_Access_Layer */
3203 
3204 
3205 /* ----------------------------------------------------------------------------
3206  -- MTB Peripheral Access Layer
3207  ---------------------------------------------------------------------------- */
3208 
3209 /*!
3210  * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
3211  * @{
3212  */
3213 
3214 /** MTB - Register Layout Typedef */
3215 typedef struct {
3216  __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
3217  __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
3218  __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
3219  __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
3220  uint8_t RESERVED_0[3824];
3221  __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
3222  uint8_t RESERVED_1[156];
3223  __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
3224  __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
3225  uint8_t RESERVED_2[8];
3226  __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
3227  __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
3228  __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
3229  __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
3230  uint8_t RESERVED_3[8];
3231  __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
3232  __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
3233  __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
3234  __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
3235 } MTB_Type, *MTB_MemMapPtr;
3236 
3237 /* ----------------------------------------------------------------------------
3238  -- MTB - Register accessor macros
3239  ---------------------------------------------------------------------------- */
3240 
3241 /*!
3242  * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
3243  * @{
3244  */
3245 
3246 
3247 /* MTB - Register accessors */
3248 #define MTB_POSITION_REG(base) ((base)->POSITION)
3249 #define MTB_MASTER_REG(base) ((base)->MASTER)
3250 #define MTB_FLOW_REG(base) ((base)->FLOW)
3251 #define MTB_BASE_REG(base) ((base)->BASE)
3252 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
3253 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
3254 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
3255 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
3256 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
3257 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
3258 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
3259 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
3260 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
3261 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
3262 #define MTB_PERIPHID_COUNT 8
3263 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
3264 #define MTB_COMPID_COUNT 4
3265 
3266 /*!
3267  * @}
3268  */ /* end of group MTB_Register_Accessor_Macros */
3269 
3270 
3271 /* ----------------------------------------------------------------------------
3272  -- MTB Register Masks
3273  ---------------------------------------------------------------------------- */
3274 
3275 /*!
3276  * @addtogroup MTB_Register_Masks MTB Register Masks
3277  * @{
3278  */
3279 
3280 /* POSITION Bit Fields */
3281 #define MTB_POSITION_WRAP_MASK 0x4u
3282 #define MTB_POSITION_WRAP_SHIFT 2
3283 #define MTB_POSITION_WRAP_WIDTH 1
3284 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_WRAP_SHIFT))&MTB_POSITION_WRAP_MASK)
3285 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
3286 #define MTB_POSITION_POINTER_SHIFT 3
3287 #define MTB_POSITION_POINTER_WIDTH 29
3288 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
3289 /* MASTER Bit Fields */
3290 #define MTB_MASTER_MASK_MASK 0x1Fu
3291 #define MTB_MASTER_MASK_SHIFT 0
3292 #define MTB_MASTER_MASK_WIDTH 5
3293 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
3294 #define MTB_MASTER_TSTARTEN_MASK 0x20u
3295 #define MTB_MASTER_TSTARTEN_SHIFT 5
3296 #define MTB_MASTER_TSTARTEN_WIDTH 1
3297 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTARTEN_SHIFT))&MTB_MASTER_TSTARTEN_MASK)
3298 #define MTB_MASTER_TSTOPEN_MASK 0x40u
3299 #define MTB_MASTER_TSTOPEN_SHIFT 6
3300 #define MTB_MASTER_TSTOPEN_WIDTH 1
3301 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_TSTOPEN_SHIFT))&MTB_MASTER_TSTOPEN_MASK)
3302 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
3303 #define MTB_MASTER_SFRWPRIV_SHIFT 7
3304 #define MTB_MASTER_SFRWPRIV_WIDTH 1
3305 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_SFRWPRIV_SHIFT))&MTB_MASTER_SFRWPRIV_MASK)
3306 #define MTB_MASTER_RAMPRIV_MASK 0x100u
3307 #define MTB_MASTER_RAMPRIV_SHIFT 8
3308 #define MTB_MASTER_RAMPRIV_WIDTH 1
3309 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_RAMPRIV_SHIFT))&MTB_MASTER_RAMPRIV_MASK)
3310 #define MTB_MASTER_HALTREQ_MASK 0x200u
3311 #define MTB_MASTER_HALTREQ_SHIFT 9
3312 #define MTB_MASTER_HALTREQ_WIDTH 1
3313 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_HALTREQ_SHIFT))&MTB_MASTER_HALTREQ_MASK)
3314 #define MTB_MASTER_EN_MASK 0x80000000u
3315 #define MTB_MASTER_EN_SHIFT 31
3316 #define MTB_MASTER_EN_WIDTH 1
3317 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_EN_SHIFT))&MTB_MASTER_EN_MASK)
3318 /* FLOW Bit Fields */
3319 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
3320 #define MTB_FLOW_AUTOSTOP_SHIFT 0
3321 #define MTB_FLOW_AUTOSTOP_WIDTH 1
3322 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOSTOP_SHIFT))&MTB_FLOW_AUTOSTOP_MASK)
3323 #define MTB_FLOW_AUTOHALT_MASK 0x2u
3324 #define MTB_FLOW_AUTOHALT_SHIFT 1
3325 #define MTB_FLOW_AUTOHALT_WIDTH 1
3326 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_AUTOHALT_SHIFT))&MTB_FLOW_AUTOHALT_MASK)
3327 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
3328 #define MTB_FLOW_WATERMARK_SHIFT 3
3329 #define MTB_FLOW_WATERMARK_WIDTH 29
3330 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
3331 /* BASE Bit Fields */
3332 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
3333 #define MTB_BASE_BASEADDR_SHIFT 0
3334 #define MTB_BASE_BASEADDR_WIDTH 32
3335 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
3336 /* MODECTRL Bit Fields */
3337 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
3338 #define MTB_MODECTRL_MODECTRL_SHIFT 0
3339 #define MTB_MODECTRL_MODECTRL_WIDTH 32
3340 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
3341 /* TAGSET Bit Fields */
3342 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
3343 #define MTB_TAGSET_TAGSET_SHIFT 0
3344 #define MTB_TAGSET_TAGSET_WIDTH 32
3345 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
3346 /* TAGCLEAR Bit Fields */
3347 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
3348 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
3349 #define MTB_TAGCLEAR_TAGCLEAR_WIDTH 32
3350 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
3351 /* LOCKACCESS Bit Fields */
3352 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
3353 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
3354 #define MTB_LOCKACCESS_LOCKACCESS_WIDTH 32
3355 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
3356 /* LOCKSTAT Bit Fields */
3357 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
3358 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
3359 #define MTB_LOCKSTAT_LOCKSTAT_WIDTH 32
3360 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
3361 /* AUTHSTAT Bit Fields */
3362 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
3363 #define MTB_AUTHSTAT_BIT0_SHIFT 0
3364 #define MTB_AUTHSTAT_BIT0_WIDTH 1
3365 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT0_SHIFT))&MTB_AUTHSTAT_BIT0_MASK)
3366 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
3367 #define MTB_AUTHSTAT_BIT1_SHIFT 1
3368 #define MTB_AUTHSTAT_BIT1_WIDTH 1
3369 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT1_SHIFT))&MTB_AUTHSTAT_BIT1_MASK)
3370 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
3371 #define MTB_AUTHSTAT_BIT2_SHIFT 2
3372 #define MTB_AUTHSTAT_BIT2_WIDTH 1
3373 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT2_SHIFT))&MTB_AUTHSTAT_BIT2_MASK)
3374 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
3375 #define MTB_AUTHSTAT_BIT3_SHIFT 3
3376 #define MTB_AUTHSTAT_BIT3_WIDTH 1
3377 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x))<<MTB_AUTHSTAT_BIT3_SHIFT))&MTB_AUTHSTAT_BIT3_MASK)
3378 /* DEVICEARCH Bit Fields */
3379 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
3380 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
3381 #define MTB_DEVICEARCH_DEVICEARCH_WIDTH 32
3382 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
3383 /* DEVICECFG Bit Fields */
3384 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
3385 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
3386 #define MTB_DEVICECFG_DEVICECFG_WIDTH 32
3387 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
3388 /* DEVICETYPID Bit Fields */
3389 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
3390 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
3391 #define MTB_DEVICETYPID_DEVICETYPID_WIDTH 32
3392 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
3393 /* PERIPHID Bit Fields */
3394 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
3395 #define MTB_PERIPHID_PERIPHID_SHIFT 0
3396 #define MTB_PERIPHID_PERIPHID_WIDTH 32
3397 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
3398 /* COMPID Bit Fields */
3399 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
3400 #define MTB_COMPID_COMPID_SHIFT 0
3401 #define MTB_COMPID_COMPID_WIDTH 32
3402 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
3403 
3404 /*!
3405  * @}
3406  */ /* end of group MTB_Register_Masks */
3407 
3408 
3409 /* MTB - Peripheral instance base addresses */
3410 /** Peripheral MTB base address */
3411 #define MTB_BASE (0xF0000000u)
3412 /** Peripheral MTB base pointer */
3413 #define MTB ((MTB_Type *)MTB_BASE)
3414 #define MTB_BASE_PTR (MTB)
3415 /** Array initializer of MTB peripheral base addresses */
3416 #define MTB_BASE_ADDRS { MTB_BASE }
3417 /** Array initializer of MTB peripheral base pointers */
3418 #define MTB_BASE_PTRS { MTB }
3419 
3420 /* ----------------------------------------------------------------------------
3421  -- MTB - Register accessor macros
3422  ---------------------------------------------------------------------------- */
3423 
3424 /*!
3425  * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
3426  * @{
3427  */
3428 
3429 
3430 /* MTB - Register instance definitions */
3431 /* MTB */
3432 #define MTB_POSITION MTB_POSITION_REG(MTB)
3433 #define MTB_MASTER MTB_MASTER_REG(MTB)
3434 #define MTB_FLOW MTB_FLOW_REG(MTB)
3435 #define MTB_BASEr MTB_BASE_REG(MTB)
3436 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
3437 #define MTB_TAGSET MTB_TAGSET_REG(MTB)
3438 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
3439 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
3440 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
3441 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
3442 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
3443 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
3444 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
3445 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
3446 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
3447 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
3448 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
3449 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
3450 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
3451 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
3452 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
3453 #define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
3454 #define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
3455 #define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
3456 #define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
3457 
3458 /* MTB - Register array accessors */
3459 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
3460 #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
3461 
3462 /*!
3463  * @}
3464  */ /* end of group MTB_Register_Accessor_Macros */
3465 
3466 
3467 /*!
3468  * @}
3469  */ /* end of group MTB_Peripheral_Access_Layer */
3470 
3471 
3472 /* ----------------------------------------------------------------------------
3473  -- MTBDWT Peripheral Access Layer
3474  ---------------------------------------------------------------------------- */
3475 
3476 /*!
3477  * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
3478  * @{
3479  */
3480 
3481 /** MTBDWT - Register Layout Typedef */
3482 typedef struct {
3483  __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
3484  uint8_t RESERVED_0[28];
3485  struct { /* offset: 0x20, array step: 0x10 */
3486  __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
3487  __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
3488  __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
3489  uint8_t RESERVED_0[4];
3490  } COMPARATOR[2];
3491  uint8_t RESERVED_1[448];
3492  __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
3493  uint8_t RESERVED_2[3524];
3494  __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
3495  __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
3496  __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
3497  __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
3498 } MTBDWT_Type, *MTBDWT_MemMapPtr;
3499 
3500 /* ----------------------------------------------------------------------------
3501  -- MTBDWT - Register accessor macros
3502  ---------------------------------------------------------------------------- */
3503 
3504 /*!
3505  * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
3506  * @{
3507  */
3508 
3509 
3510 /* MTBDWT - Register accessors */
3511 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
3512 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
3513 #define MTBDWT_COMP_COUNT 2
3514 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
3515 #define MTBDWT_MASK_COUNT 2
3516 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
3517 #define MTBDWT_FCT_COUNT 2
3518 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
3519 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
3520 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
3521 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
3522 #define MTBDWT_PERIPHID_COUNT 8
3523 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
3524 #define MTBDWT_COMPID_COUNT 4
3525 
3526 /*!
3527  * @}
3528  */ /* end of group MTBDWT_Register_Accessor_Macros */
3529 
3530 
3531 /* ----------------------------------------------------------------------------
3532  -- MTBDWT Register Masks
3533  ---------------------------------------------------------------------------- */
3534 
3535 /*!
3536  * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
3537  * @{
3538  */
3539 
3540 /* CTRL Bit Fields */
3541 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
3542 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
3543 #define MTBDWT_CTRL_DWTCFGCTRL_WIDTH 28
3544 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
3545 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
3546 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
3547 #define MTBDWT_CTRL_NUMCMP_WIDTH 4
3548 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
3549 /* COMP Bit Fields */
3550 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
3551 #define MTBDWT_COMP_COMP_SHIFT 0
3552 #define MTBDWT_COMP_COMP_WIDTH 32
3553 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
3554 /* MASK Bit Fields */
3555 #define MTBDWT_MASK_MASK_MASK 0x1Fu
3556 #define MTBDWT_MASK_MASK_SHIFT 0
3557 #define MTBDWT_MASK_MASK_WIDTH 5
3558 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
3559 /* FCT Bit Fields */
3560 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
3561 #define MTBDWT_FCT_FUNCTION_SHIFT 0
3562 #define MTBDWT_FCT_FUNCTION_WIDTH 4
3563 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
3564 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
3565 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
3566 #define MTBDWT_FCT_DATAVMATCH_WIDTH 1
3567 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVMATCH_SHIFT))&MTBDWT_FCT_DATAVMATCH_MASK)
3568 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
3569 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
3570 #define MTBDWT_FCT_DATAVSIZE_WIDTH 2
3571 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
3572 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
3573 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
3574 #define MTBDWT_FCT_DATAVADDR0_WIDTH 4
3575 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
3576 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
3577 #define MTBDWT_FCT_MATCHED_SHIFT 24
3578 #define MTBDWT_FCT_MATCHED_WIDTH 1
3579 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_MATCHED_SHIFT))&MTBDWT_FCT_MATCHED_MASK)
3580 /* TBCTRL Bit Fields */
3581 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
3582 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
3583 #define MTBDWT_TBCTRL_ACOMP0_WIDTH 1
3584 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_ACOMP0_SHIFT))&MTBDWT_TBCTRL_ACOMP0_MASK)
3585 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
3586 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
3587 #define MTBDWT_TBCTRL_ACOMP1_WIDTH 1
3588 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_ACOMP1_SHIFT))&MTBDWT_TBCTRL_ACOMP1_MASK)
3589 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
3590 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
3591 #define MTBDWT_TBCTRL_NUMCOMP_WIDTH 4
3592 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
3593 /* DEVICECFG Bit Fields */
3594 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
3595 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
3596 #define MTBDWT_DEVICECFG_DEVICECFG_WIDTH 32
3597 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
3598 /* DEVICETYPID Bit Fields */
3599 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
3600 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
3601 #define MTBDWT_DEVICETYPID_DEVICETYPID_WIDTH 32
3602 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
3603 /* PERIPHID Bit Fields */
3604 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
3605 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
3606 #define MTBDWT_PERIPHID_PERIPHID_WIDTH 32
3607 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
3608 /* COMPID Bit Fields */
3609 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
3610 #define MTBDWT_COMPID_COMPID_SHIFT 0
3611 #define MTBDWT_COMPID_COMPID_WIDTH 32
3612 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
3613 
3614 /*!
3615  * @}
3616  */ /* end of group MTBDWT_Register_Masks */
3617 
3618 
3619 /* MTBDWT - Peripheral instance base addresses */
3620 /** Peripheral MTBDWT base address */
3621 #define MTBDWT_BASE (0xF0001000u)
3622 /** Peripheral MTBDWT base pointer */
3623 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
3624 #define MTBDWT_BASE_PTR (MTBDWT)
3625 /** Array initializer of MTBDWT peripheral base addresses */
3626 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
3627 /** Array initializer of MTBDWT peripheral base pointers */
3628 #define MTBDWT_BASE_PTRS { MTBDWT }
3629 
3630 /* ----------------------------------------------------------------------------
3631  -- MTBDWT - Register accessor macros
3632  ---------------------------------------------------------------------------- */
3633 
3634 /*!
3635  * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
3636  * @{
3637  */
3638 
3639 
3640 /* MTBDWT - Register instance definitions */
3641 /* MTBDWT */
3642 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
3643 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
3644 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
3645 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
3646 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
3647 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
3648 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
3649 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
3650 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
3651 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
3652 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
3653 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
3654 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
3655 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
3656 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
3657 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
3658 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
3659 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
3660 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
3661 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
3662 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
3663 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
3664 
3665 /* MTBDWT - Register array accessors */
3666 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
3667 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
3668 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
3669 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
3670 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
3671 
3672 /*!
3673  * @}
3674  */ /* end of group MTBDWT_Register_Accessor_Macros */
3675 
3676 
3677 /*!
3678  * @}
3679  */ /* end of group MTBDWT_Peripheral_Access_Layer */
3680 
3681 
3682 /* ----------------------------------------------------------------------------
3683  -- NV Peripheral Access Layer
3684  ---------------------------------------------------------------------------- */
3685 
3686 /*!
3687  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
3688  * @{
3689  */
3690 
3691 /** NV - Register Layout Typedef */
3692 typedef struct {
3693  __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
3694  __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
3695  __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
3696  __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
3697  __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
3698  __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
3699  __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
3700  __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
3701  __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
3702  __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
3703  __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
3704  __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
3705  __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
3706  __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
3707 } NV_Type, *NV_MemMapPtr;
3708 
3709 /* ----------------------------------------------------------------------------
3710  -- NV - Register accessor macros
3711  ---------------------------------------------------------------------------- */
3712 
3713 /*!
3714  * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
3715  * @{
3716  */
3717 
3718 
3719 /* NV - Register accessors */
3720 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
3721 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
3722 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
3723 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
3724 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
3725 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
3726 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
3727 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
3728 #define NV_FPROT3_REG(base) ((base)->FPROT3)
3729 #define NV_FPROT2_REG(base) ((base)->FPROT2)
3730 #define NV_FPROT1_REG(base) ((base)->FPROT1)
3731 #define NV_FPROT0_REG(base) ((base)->FPROT0)
3732 #define NV_FSEC_REG(base) ((base)->FSEC)
3733 #define NV_FOPT_REG(base) ((base)->FOPT)
3734 
3735 /*!
3736  * @}
3737  */ /* end of group NV_Register_Accessor_Macros */
3738 
3739 
3740 /* ----------------------------------------------------------------------------
3741  -- NV Register Masks
3742  ---------------------------------------------------------------------------- */
3743 
3744 /*!
3745  * @addtogroup NV_Register_Masks NV Register Masks
3746  * @{
3747  */
3748 
3749 /* BACKKEY3 Bit Fields */
3750 #define NV_BACKKEY3_KEY_MASK 0xFFu
3751 #define NV_BACKKEY3_KEY_SHIFT 0
3752 #define NV_BACKKEY3_KEY_WIDTH 8
3753 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
3754 /* BACKKEY2 Bit Fields */
3755 #define NV_BACKKEY2_KEY_MASK 0xFFu
3756 #define NV_BACKKEY2_KEY_SHIFT 0
3757 #define NV_BACKKEY2_KEY_WIDTH 8
3758 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
3759 /* BACKKEY1 Bit Fields */
3760 #define NV_BACKKEY1_KEY_MASK 0xFFu
3761 #define NV_BACKKEY1_KEY_SHIFT 0
3762 #define NV_BACKKEY1_KEY_WIDTH 8
3763 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
3764 /* BACKKEY0 Bit Fields */
3765 #define NV_BACKKEY0_KEY_MASK 0xFFu
3766 #define NV_BACKKEY0_KEY_SHIFT 0
3767 #define NV_BACKKEY0_KEY_WIDTH 8
3768 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
3769 /* BACKKEY7 Bit Fields */
3770 #define NV_BACKKEY7_KEY_MASK 0xFFu
3771 #define NV_BACKKEY7_KEY_SHIFT 0
3772 #define NV_BACKKEY7_KEY_WIDTH 8
3773 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
3774 /* BACKKEY6 Bit Fields */
3775 #define NV_BACKKEY6_KEY_MASK 0xFFu
3776 #define NV_BACKKEY6_KEY_SHIFT 0
3777 #define NV_BACKKEY6_KEY_WIDTH 8
3778 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
3779 /* BACKKEY5 Bit Fields */
3780 #define NV_BACKKEY5_KEY_MASK 0xFFu
3781 #define NV_BACKKEY5_KEY_SHIFT 0
3782 #define NV_BACKKEY5_KEY_WIDTH 8
3783 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
3784 /* BACKKEY4 Bit Fields */
3785 #define NV_BACKKEY4_KEY_MASK 0xFFu
3786 #define NV_BACKKEY4_KEY_SHIFT 0
3787 #define NV_BACKKEY4_KEY_WIDTH 8
3788 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
3789 /* FPROT3 Bit Fields */
3790 #define NV_FPROT3_PROT_MASK 0xFFu
3791 #define NV_FPROT3_PROT_SHIFT 0
3792 #define NV_FPROT3_PROT_WIDTH 8
3793 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
3794 /* FPROT2 Bit Fields */
3795 #define NV_FPROT2_PROT_MASK 0xFFu
3796 #define NV_FPROT2_PROT_SHIFT 0
3797 #define NV_FPROT2_PROT_WIDTH 8
3798 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
3799 /* FPROT1 Bit Fields */
3800 #define NV_FPROT1_PROT_MASK 0xFFu
3801 #define NV_FPROT1_PROT_SHIFT 0
3802 #define NV_FPROT1_PROT_WIDTH 8
3803 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
3804 /* FPROT0 Bit Fields */
3805 #define NV_FPROT0_PROT_MASK 0xFFu
3806 #define NV_FPROT0_PROT_SHIFT 0
3807 #define NV_FPROT0_PROT_WIDTH 8
3808 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
3809 /* FSEC Bit Fields */
3810 #define NV_FSEC_SEC_MASK 0x3u
3811 #define NV_FSEC_SEC_SHIFT 0
3812 #define NV_FSEC_SEC_WIDTH 2
3813 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
3814 #define NV_FSEC_FSLACC_MASK 0xCu
3815 #define NV_FSEC_FSLACC_SHIFT 2
3816 #define NV_FSEC_FSLACC_WIDTH 2
3817 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
3818 #define NV_FSEC_MEEN_MASK 0x30u
3819 #define NV_FSEC_MEEN_SHIFT 4
3820 #define NV_FSEC_MEEN_WIDTH 2
3821 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
3822 #define NV_FSEC_KEYEN_MASK 0xC0u
3823 #define NV_FSEC_KEYEN_SHIFT 6
3824 #define NV_FSEC_KEYEN_WIDTH 2
3825 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
3826 /* FOPT Bit Fields */
3827 #define NV_FOPT_LPBOOT0_MASK 0x1u
3828 #define NV_FOPT_LPBOOT0_SHIFT 0
3829 #define NV_FOPT_LPBOOT0_WIDTH 1
3830 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT0_SHIFT))&NV_FOPT_LPBOOT0_MASK)
3831 #define NV_FOPT_NMI_DIS_MASK 0x4u
3832 #define NV_FOPT_NMI_DIS_SHIFT 2
3833 #define NV_FOPT_NMI_DIS_WIDTH 1
3834 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
3835 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
3836 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
3837 #define NV_FOPT_RESET_PIN_CFG_WIDTH 1
3838 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_RESET_PIN_CFG_SHIFT))&NV_FOPT_RESET_PIN_CFG_MASK)
3839 #define NV_FOPT_LPBOOT1_MASK 0x10u
3840 #define NV_FOPT_LPBOOT1_SHIFT 4
3841 #define NV_FOPT_LPBOOT1_WIDTH 1
3842 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT1_SHIFT))&NV_FOPT_LPBOOT1_MASK)
3843 #define NV_FOPT_FAST_INIT_MASK 0x20u
3844 #define NV_FOPT_FAST_INIT_SHIFT 5
3845 #define NV_FOPT_FAST_INIT_WIDTH 1
3846 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
3847 
3848 /*!
3849  * @}
3850  */ /* end of group NV_Register_Masks */
3851 
3852 
3853 /* NV - Peripheral instance base addresses */
3854 /** Peripheral FTFA_FlashConfig base address */
3855 #define FTFA_FlashConfig_BASE (0x400u)
3856 /** Peripheral FTFA_FlashConfig base pointer */
3857 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
3858 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
3859 /** Array initializer of NV peripheral base addresses */
3860 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
3861 /** Array initializer of NV peripheral base pointers */
3862 #define NV_BASE_PTRS { FTFA_FlashConfig }
3863 
3864 /* ----------------------------------------------------------------------------
3865  -- NV - Register accessor macros
3866  ---------------------------------------------------------------------------- */
3867 
3868 /*!
3869  * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
3870  * @{
3871  */
3872 
3873 
3874 /* NV - Register instance definitions */
3875 /* FTFA_FlashConfig */
3876 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
3877 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
3878 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
3879 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
3880 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
3881 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
3882 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
3883 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
3884 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
3885 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
3886 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
3887 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
3888 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
3889 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
3890 
3891 /*!
3892  * @}
3893  */ /* end of group NV_Register_Accessor_Macros */
3894 
3895 
3896 /*!
3897  * @}
3898  */ /* end of group NV_Peripheral_Access_Layer */
3899 
3900 
3901 /* ----------------------------------------------------------------------------
3902  -- OSC Peripheral Access Layer
3903  ---------------------------------------------------------------------------- */
3904 
3905 /*!
3906  * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
3907  * @{
3908  */
3909 
3910 /** OSC - Register Layout Typedef */
3911 typedef struct {
3912  __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
3913 } OSC_Type, *OSC_MemMapPtr;
3914 
3915 /* ----------------------------------------------------------------------------
3916  -- OSC - Register accessor macros
3917  ---------------------------------------------------------------------------- */
3918 
3919 /*!
3920  * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
3921  * @{
3922  */
3923 
3924 
3925 /* OSC - Register accessors */
3926 #define OSC_CR_REG(base) ((base)->CR)
3927 
3928 /*!
3929  * @}
3930  */ /* end of group OSC_Register_Accessor_Macros */
3931 
3932 
3933 /* ----------------------------------------------------------------------------
3934  -- OSC Register Masks
3935  ---------------------------------------------------------------------------- */
3936 
3937 /*!
3938  * @addtogroup OSC_Register_Masks OSC Register Masks
3939  * @{
3940  */
3941 
3942 /* CR Bit Fields */
3943 #define OSC_CR_SC16P_MASK 0x1u
3944 #define OSC_CR_SC16P_SHIFT 0
3945 #define OSC_CR_SC16P_WIDTH 1
3946 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
3947 #define OSC_CR_SC8P_MASK 0x2u
3948 #define OSC_CR_SC8P_SHIFT 1
3949 #define OSC_CR_SC8P_WIDTH 1
3950 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
3951 #define OSC_CR_SC4P_MASK 0x4u
3952 #define OSC_CR_SC4P_SHIFT 2
3953 #define OSC_CR_SC4P_WIDTH 1
3954 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
3955 #define OSC_CR_SC2P_MASK 0x8u
3956 #define OSC_CR_SC2P_SHIFT 3
3957 #define OSC_CR_SC2P_WIDTH 1
3958 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
3959 #define OSC_CR_EREFSTEN_MASK 0x20u
3960 #define OSC_CR_EREFSTEN_SHIFT 5
3961 #define OSC_CR_EREFSTEN_WIDTH 1
3962 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
3963 #define OSC_CR_ERCLKEN_MASK 0x80u
3964 #define OSC_CR_ERCLKEN_SHIFT 7
3965 #define OSC_CR_ERCLKEN_WIDTH 1
3966 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
3967 
3968 /*!
3969  * @}
3970  */ /* end of group OSC_Register_Masks */
3971 
3972 
3973 /* OSC - Peripheral instance base addresses */
3974 /** Peripheral OSC0 base address */
3975 #define OSC0_BASE (0x40065000u)
3976 /** Peripheral OSC0 base pointer */
3977 #define OSC0 ((OSC_Type *)OSC0_BASE)
3978 #define OSC0_BASE_PTR (OSC0)
3979 /** Array initializer of OSC peripheral base addresses */
3980 #define OSC_BASE_ADDRS { OSC0_BASE }
3981 /** Array initializer of OSC peripheral base pointers */
3982 #define OSC_BASE_PTRS { OSC0 }
3983 
3984 /* ----------------------------------------------------------------------------
3985  -- OSC - Register accessor macros
3986  ---------------------------------------------------------------------------- */
3987 
3988 /*!
3989  * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
3990  * @{
3991  */
3992 
3993 
3994 /* OSC - Register instance definitions */
3995 /* OSC0 */
3996 #define OSC0_CR OSC_CR_REG(OSC0)
3997 
3998 /*!
3999  * @}
4000  */ /* end of group OSC_Register_Accessor_Macros */
4001 
4002 
4003 /*!
4004  * @}
4005  */ /* end of group OSC_Peripheral_Access_Layer */
4006 
4007 
4008 /* ----------------------------------------------------------------------------
4009  -- PIT Peripheral Access Layer
4010  ---------------------------------------------------------------------------- */
4011 
4012 /*!
4013  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
4014  * @{
4015  */
4016 
4017 /** PIT - Register Layout Typedef */
4018 typedef struct {
4019  __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
4020  uint8_t RESERVED_0[220];
4021  __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
4022  __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
4023  uint8_t RESERVED_1[24];
4024  struct { /* offset: 0x100, array step: 0x10 */
4025  __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
4026  __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
4027  __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
4028  __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
4029  } CHANNEL[2];
4030 } PIT_Type, *PIT_MemMapPtr;
4031 
4032 /* ----------------------------------------------------------------------------
4033  -- PIT - Register accessor macros
4034  ---------------------------------------------------------------------------- */
4035 
4036 /*!
4037  * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
4038  * @{
4039  */
4040 
4041 
4042 /* PIT - Register accessors */
4043 #define PIT_MCR_REG(base) ((base)->MCR)
4044 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
4045 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
4046 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
4047 #define PIT_LDVAL_COUNT 2
4048 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
4049 #define PIT_CVAL_COUNT 2
4050 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
4051 #define PIT_TCTRL_COUNT 2
4052 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
4053 #define PIT_TFLG_COUNT 2
4054 
4055 /*!
4056  * @}
4057  */ /* end of group PIT_Register_Accessor_Macros */
4058 
4059 
4060 /* ----------------------------------------------------------------------------
4061  -- PIT Register Masks
4062  ---------------------------------------------------------------------------- */
4063 
4064 /*!
4065  * @addtogroup PIT_Register_Masks PIT Register Masks
4066  * @{
4067  */
4068 
4069 /* MCR Bit Fields */
4070 #define PIT_MCR_FRZ_MASK 0x1u
4071 #define PIT_MCR_FRZ_SHIFT 0
4072 #define PIT_MCR_FRZ_WIDTH 1
4073 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
4074 #define PIT_MCR_MDIS_MASK 0x2u
4075 #define PIT_MCR_MDIS_SHIFT 1
4076 #define PIT_MCR_MDIS_WIDTH 1
4077 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
4078 /* LTMR64H Bit Fields */
4079 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
4080 #define PIT_LTMR64H_LTH_SHIFT 0
4081 #define PIT_LTMR64H_LTH_WIDTH 32
4082 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
4083 /* LTMR64L Bit Fields */
4084 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
4085 #define PIT_LTMR64L_LTL_SHIFT 0
4086 #define PIT_LTMR64L_LTL_WIDTH 32
4087 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
4088 /* LDVAL Bit Fields */
4089 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
4090 #define PIT_LDVAL_TSV_SHIFT 0
4091 #define PIT_LDVAL_TSV_WIDTH 32
4092 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
4093 /* CVAL Bit Fields */
4094 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
4095 #define PIT_CVAL_TVL_SHIFT 0
4096 #define PIT_CVAL_TVL_WIDTH 32
4097 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
4098 /* TCTRL Bit Fields */
4099 #define PIT_TCTRL_TEN_MASK 0x1u
4100 #define PIT_TCTRL_TEN_SHIFT 0
4101 #define PIT_TCTRL_TEN_WIDTH 1
4102 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
4103 #define PIT_TCTRL_TIE_MASK 0x2u
4104 #define PIT_TCTRL_TIE_SHIFT 1
4105 #define PIT_TCTRL_TIE_WIDTH 1
4106 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
4107 #define PIT_TCTRL_CHN_MASK 0x4u
4108 #define PIT_TCTRL_CHN_SHIFT 2
4109 #define PIT_TCTRL_CHN_WIDTH 1
4110 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
4111 /* TFLG Bit Fields */
4112 #define PIT_TFLG_TIF_MASK 0x1u
4113 #define PIT_TFLG_TIF_SHIFT 0
4114 #define PIT_TFLG_TIF_WIDTH 1
4115 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
4116 
4117 /*!
4118  * @}
4119  */ /* end of group PIT_Register_Masks */
4120 
4121 
4122 /* PIT - Peripheral instance base addresses */
4123 /** Peripheral PIT base address */
4124 #define PIT_BASE (0x40037000u)
4125 /** Peripheral PIT base pointer */
4126 #define PIT ((PIT_Type *)PIT_BASE)
4127 #define PIT_BASE_PTR (PIT)
4128 /** Array initializer of PIT peripheral base addresses */
4129 #define PIT_BASE_ADDRS { PIT_BASE }
4130 /** Array initializer of PIT peripheral base pointers */
4131 #define PIT_BASE_PTRS { PIT }
4132 /** Interrupt vectors for the PIT peripheral type */
4133 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
4134 
4135 /* ----------------------------------------------------------------------------
4136  -- PIT - Register accessor macros
4137  ---------------------------------------------------------------------------- */
4138 
4139 /*!
4140  * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
4141  * @{
4142  */
4143 
4144 
4145 /* PIT - Register instance definitions */
4146 /* PIT */
4147 #define PIT_MCR PIT_MCR_REG(PIT)
4148 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
4149 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
4150 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
4151 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
4152 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
4153 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
4154 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
4155 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
4156 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
4157 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
4158 
4159 /* PIT - Register array accessors */
4160 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
4161 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
4162 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
4163 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
4164 
4165 /*!
4166  * @}
4167  */ /* end of group PIT_Register_Accessor_Macros */
4168 
4169 
4170 /*!
4171  * @}
4172  */ /* end of group PIT_Peripheral_Access_Layer */
4173 
4174 
4175 /* ----------------------------------------------------------------------------
4176  -- PMC Peripheral Access Layer
4177  ---------------------------------------------------------------------------- */
4178 
4179 /*!
4180  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
4181  * @{
4182  */
4183 
4184 /** PMC - Register Layout Typedef */
4185 typedef struct {
4186  __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
4187  __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
4188  __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
4189 } PMC_Type, *PMC_MemMapPtr;
4190 
4191 /* ----------------------------------------------------------------------------
4192  -- PMC - Register accessor macros
4193  ---------------------------------------------------------------------------- */
4194 
4195 /*!
4196  * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
4197  * @{
4198  */
4199 
4200 
4201 /* PMC - Register accessors */
4202 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
4203 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
4204 #define PMC_REGSC_REG(base) ((base)->REGSC)
4205 
4206 /*!
4207  * @}
4208  */ /* end of group PMC_Register_Accessor_Macros */
4209 
4210 
4211 /* ----------------------------------------------------------------------------
4212  -- PMC Register Masks
4213  ---------------------------------------------------------------------------- */
4214 
4215 /*!
4216  * @addtogroup PMC_Register_Masks PMC Register Masks
4217  * @{
4218  */
4219 
4220 /* LVDSC1 Bit Fields */
4221 #define PMC_LVDSC1_LVDV_MASK 0x3u
4222 #define PMC_LVDSC1_LVDV_SHIFT 0
4223 #define PMC_LVDSC1_LVDV_WIDTH 2
4224 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
4225 #define PMC_LVDSC1_LVDRE_MASK 0x10u
4226 #define PMC_LVDSC1_LVDRE_SHIFT 4
4227 #define PMC_LVDSC1_LVDRE_WIDTH 1
4228 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
4229 #define PMC_LVDSC1_LVDIE_MASK 0x20u
4230 #define PMC_LVDSC1_LVDIE_SHIFT 5
4231 #define PMC_LVDSC1_LVDIE_WIDTH 1
4232 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
4233 #define PMC_LVDSC1_LVDACK_MASK 0x40u
4234 #define PMC_LVDSC1_LVDACK_SHIFT 6
4235 #define PMC_LVDSC1_LVDACK_WIDTH 1
4236 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
4237 #define PMC_LVDSC1_LVDF_MASK 0x80u
4238 #define PMC_LVDSC1_LVDF_SHIFT 7
4239 #define PMC_LVDSC1_LVDF_WIDTH 1
4240 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
4241 /* LVDSC2 Bit Fields */
4242 #define PMC_LVDSC2_LVWV_MASK 0x3u
4243 #define PMC_LVDSC2_LVWV_SHIFT 0
4244 #define PMC_LVDSC2_LVWV_WIDTH 2
4245 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
4246 #define PMC_LVDSC2_LVWIE_MASK 0x20u
4247 #define PMC_LVDSC2_LVWIE_SHIFT 5
4248 #define PMC_LVDSC2_LVWIE_WIDTH 1
4249 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
4250 #define PMC_LVDSC2_LVWACK_MASK 0x40u
4251 #define PMC_LVDSC2_LVWACK_SHIFT 6
4252 #define PMC_LVDSC2_LVWACK_WIDTH 1
4253 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
4254 #define PMC_LVDSC2_LVWF_MASK 0x80u
4255 #define PMC_LVDSC2_LVWF_SHIFT 7
4256 #define PMC_LVDSC2_LVWF_WIDTH 1
4257 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
4258 /* REGSC Bit Fields */
4259 #define PMC_REGSC_BGBE_MASK 0x1u
4260 #define PMC_REGSC_BGBE_SHIFT 0
4261 #define PMC_REGSC_BGBE_WIDTH 1
4262 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
4263 #define PMC_REGSC_REGONS_MASK 0x4u
4264 #define PMC_REGSC_REGONS_SHIFT 2
4265 #define PMC_REGSC_REGONS_WIDTH 1
4266 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
4267 #define PMC_REGSC_ACKISO_MASK 0x8u
4268 #define PMC_REGSC_ACKISO_SHIFT 3
4269 #define PMC_REGSC_ACKISO_WIDTH 1
4270 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
4271 #define PMC_REGSC_BGEN_MASK 0x10u
4272 #define PMC_REGSC_BGEN_SHIFT 4
4273 #define PMC_REGSC_BGEN_WIDTH 1
4274 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
4275 
4276 /*!
4277  * @}
4278  */ /* end of group PMC_Register_Masks */
4279 
4280 
4281 /* PMC - Peripheral instance base addresses */
4282 /** Peripheral PMC base address */
4283 #define PMC_BASE (0x4007D000u)
4284 /** Peripheral PMC base pointer */
4285 #define PMC ((PMC_Type *)PMC_BASE)
4286 #define PMC_BASE_PTR (PMC)
4287 /** Array initializer of PMC peripheral base addresses */
4288 #define PMC_BASE_ADDRS { PMC_BASE }
4289 /** Array initializer of PMC peripheral base pointers */
4290 #define PMC_BASE_PTRS { PMC }
4291 /** Interrupt vectors for the PMC peripheral type */
4292 #define PMC_IRQS { LVD_LVW_IRQn }
4293 
4294 /* ----------------------------------------------------------------------------
4295  -- PMC - Register accessor macros
4296  ---------------------------------------------------------------------------- */
4297 
4298 /*!
4299  * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
4300  * @{
4301  */
4302 
4303 
4304 /* PMC - Register instance definitions */
4305 /* PMC */
4306 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
4307 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
4308 #define PMC_REGSC PMC_REGSC_REG(PMC)
4309 
4310 /*!
4311  * @}
4312  */ /* end of group PMC_Register_Accessor_Macros */
4313 
4314 
4315 /*!
4316  * @}
4317  */ /* end of group PMC_Peripheral_Access_Layer */
4318 
4319 
4320 /* ----------------------------------------------------------------------------
4321  -- PORT Peripheral Access Layer
4322  ---------------------------------------------------------------------------- */
4323 
4324 /*!
4325  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
4326  * @{
4327  */
4328 
4329 /** PORT - Register Layout Typedef */
4330 typedef struct {
4331  __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
4332  __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
4333  __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
4334  uint8_t RESERVED_0[24];
4335  __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
4336 } PORT_Type, *PORT_MemMapPtr;
4337 
4338 /* ----------------------------------------------------------------------------
4339  -- PORT - Register accessor macros
4340  ---------------------------------------------------------------------------- */
4341 
4342 /*!
4343  * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
4344  * @{
4345  */
4346 
4347 
4348 /* PORT - Register accessors */
4349 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
4350 #define PORT_PCR_COUNT 32
4351 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
4352 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
4353 #define PORT_ISFR_REG(base) ((base)->ISFR)
4354 
4355 /*!
4356  * @}
4357  */ /* end of group PORT_Register_Accessor_Macros */
4358 
4359 
4360 /* ----------------------------------------------------------------------------
4361  -- PORT Register Masks
4362  ---------------------------------------------------------------------------- */
4363 
4364 /*!
4365  * @addtogroup PORT_Register_Masks PORT Register Masks
4366  * @{
4367  */
4368 
4369 /* PCR Bit Fields */
4370 #define PORT_PCR_PS_MASK 0x1u
4371 #define PORT_PCR_PS_SHIFT 0
4372 #define PORT_PCR_PS_WIDTH 1
4373 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
4374 #define PORT_PCR_PE_MASK 0x2u
4375 #define PORT_PCR_PE_SHIFT 1
4376 #define PORT_PCR_PE_WIDTH 1
4377 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
4378 #define PORT_PCR_SRE_MASK 0x4u
4379 #define PORT_PCR_SRE_SHIFT 2
4380 #define PORT_PCR_SRE_WIDTH 1
4381 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
4382 #define PORT_PCR_PFE_MASK 0x10u
4383 #define PORT_PCR_PFE_SHIFT 4
4384 #define PORT_PCR_PFE_WIDTH 1
4385 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
4386 #define PORT_PCR_DSE_MASK 0x40u
4387 #define PORT_PCR_DSE_SHIFT 6
4388 #define PORT_PCR_DSE_WIDTH 1
4389 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
4390 #define PORT_PCR_MUX_MASK 0x700u
4391 #define PORT_PCR_MUX_SHIFT 8
4392 #define PORT_PCR_MUX_WIDTH 3
4393 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
4394 #define PORT_PCR_IRQC_MASK 0xF0000u
4395 #define PORT_PCR_IRQC_SHIFT 16
4396 #define PORT_PCR_IRQC_WIDTH 4
4397 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
4398 #define PORT_PCR_ISF_MASK 0x1000000u
4399 #define PORT_PCR_ISF_SHIFT 24
4400 #define PORT_PCR_ISF_WIDTH 1
4401 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
4402 /* GPCLR Bit Fields */
4403 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
4404 #define PORT_GPCLR_GPWD_SHIFT 0
4405 #define PORT_GPCLR_GPWD_WIDTH 16
4406 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
4407 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
4408 #define PORT_GPCLR_GPWE_SHIFT 16
4409 #define PORT_GPCLR_GPWE_WIDTH 16
4410 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
4411 /* GPCHR Bit Fields */
4412 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
4413 #define PORT_GPCHR_GPWD_SHIFT 0
4414 #define PORT_GPCHR_GPWD_WIDTH 16
4415 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
4416 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
4417 #define PORT_GPCHR_GPWE_SHIFT 16
4418 #define PORT_GPCHR_GPWE_WIDTH 16
4419 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
4420 /* ISFR Bit Fields */
4421 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
4422 #define PORT_ISFR_ISF_SHIFT 0
4423 #define PORT_ISFR_ISF_WIDTH 32
4424 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
4425 
4426 /*!
4427  * @}
4428  */ /* end of group PORT_Register_Masks */
4429 
4430 
4431 /* PORT - Peripheral instance base addresses */
4432 /** Peripheral PORTA base address */
4433 #define PORTA_BASE (0x40049000u)
4434 /** Peripheral PORTA base pointer */
4435 #define PORTA ((PORT_Type *)PORTA_BASE)
4436 #define PORTA_BASE_PTR (PORTA)
4437 /** Peripheral PORTB base address */
4438 #define PORTB_BASE (0x4004A000u)
4439 /** Peripheral PORTB base pointer */
4440 #define PORTB ((PORT_Type *)PORTB_BASE)
4441 #define PORTB_BASE_PTR (PORTB)
4442 /** Peripheral PORTC base address */
4443 #define PORTC_BASE (0x4004B000u)
4444 /** Peripheral PORTC base pointer */
4445 #define PORTC ((PORT_Type *)PORTC_BASE)
4446 #define PORTC_BASE_PTR (PORTC)
4447 /** Peripheral PORTD base address */
4448 #define PORTD_BASE (0x4004C000u)
4449 /** Peripheral PORTD base pointer */
4450 #define PORTD ((PORT_Type *)PORTD_BASE)
4451 #define PORTD_BASE_PTR (PORTD)
4452 /** Peripheral PORTE base address */
4453 #define PORTE_BASE (0x4004D000u)
4454 /** Peripheral PORTE base pointer */
4455 #define PORTE ((PORT_Type *)PORTE_BASE)
4456 #define PORTE_BASE_PTR (PORTE)
4457 /** Array initializer of PORT peripheral base addresses */
4458 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
4459 /** Array initializer of PORT peripheral base pointers */
4460 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
4461 /** Interrupt vectors for the PORT peripheral type */
4462 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, NotAvail_IRQn, PORTD_IRQn, NotAvail_IRQn }
4463 
4464 /* ----------------------------------------------------------------------------
4465  -- PORT - Register accessor macros
4466  ---------------------------------------------------------------------------- */
4467 
4468 /*!
4469  * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
4470  * @{
4471  */
4472 
4473 
4474 /* PORT - Register instance definitions */
4475 /* PORTA */
4476 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
4477 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
4478 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
4479 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
4480 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
4481 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
4482 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
4483 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
4484 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
4485 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
4486 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
4487 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
4488 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
4489 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
4490 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
4491 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
4492 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
4493 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
4494 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
4495 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
4496 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
4497 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
4498 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
4499 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
4500 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
4501 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
4502 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
4503 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
4504 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
4505 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
4506 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
4507 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
4508 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
4509 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
4510 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
4511 /* PORTB */
4512 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
4513 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
4514 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
4515 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
4516 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
4517 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
4518 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
4519 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
4520 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
4521 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
4522 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
4523 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
4524 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
4525 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
4526 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
4527 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
4528 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
4529 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
4530 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
4531 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
4532 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
4533 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
4534 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
4535 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
4536 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
4537 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
4538 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
4539 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
4540 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
4541 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
4542 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
4543 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
4544 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
4545 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
4546 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
4547 /* PORTC */
4548 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
4549 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
4550 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
4551 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
4552 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
4553 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
4554 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
4555 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
4556 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
4557 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
4558 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
4559 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
4560 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
4561 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
4562 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
4563 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
4564 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
4565 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
4566 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
4567 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
4568 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
4569 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
4570 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
4571 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
4572 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
4573 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
4574 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
4575 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
4576 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
4577 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
4578 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
4579 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
4580 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
4581 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
4582 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
4583 /* PORTD */
4584 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
4585 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
4586 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
4587 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
4588 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
4589 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
4590 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
4591 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
4592 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
4593 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
4594 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
4595 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
4596 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
4597 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
4598 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
4599 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
4600 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
4601 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
4602 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
4603 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
4604 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
4605 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
4606 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
4607 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
4608 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
4609 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
4610 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
4611 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
4612 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
4613 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
4614 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
4615 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
4616 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
4617 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
4618 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
4619 /* PORTE */
4620 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
4621 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
4622 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
4623 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
4624 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
4625 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
4626 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
4627 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
4628 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
4629 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
4630 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
4631 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
4632 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
4633 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
4634 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
4635 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
4636 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
4637 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
4638 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
4639 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
4640 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
4641 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
4642 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
4643 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
4644 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
4645 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
4646 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
4647 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
4648 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
4649 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
4650 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
4651 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
4652 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
4653 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
4654 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
4655 
4656 /* PORT - Register array accessors */
4657 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
4658 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
4659 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
4660 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
4661 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
4662 
4663 /*!
4664  * @}
4665  */ /* end of group PORT_Register_Accessor_Macros */
4666 
4667 
4668 /*!
4669  * @}
4670  */ /* end of group PORT_Peripheral_Access_Layer */
4671 
4672 
4673 /* ----------------------------------------------------------------------------
4674  -- RCM Peripheral Access Layer
4675  ---------------------------------------------------------------------------- */
4676 
4677 /*!
4678  * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
4679  * @{
4680  */
4681 
4682 /** RCM - Register Layout Typedef */
4683 typedef struct {
4684  __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
4685  __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
4686  uint8_t RESERVED_0[2];
4687  __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
4688  __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
4689 } RCM_Type, *RCM_MemMapPtr;
4690 
4691 /* ----------------------------------------------------------------------------
4692  -- RCM - Register accessor macros
4693  ---------------------------------------------------------------------------- */
4694 
4695 /*!
4696  * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
4697  * @{
4698  */
4699 
4700 
4701 /* RCM - Register accessors */
4702 #define RCM_SRS0_REG(base) ((base)->SRS0)
4703 #define RCM_SRS1_REG(base) ((base)->SRS1)
4704 #define RCM_RPFC_REG(base) ((base)->RPFC)
4705 #define RCM_RPFW_REG(base) ((base)->RPFW)
4706 
4707 /*!
4708  * @}
4709  */ /* end of group RCM_Register_Accessor_Macros */
4710 
4711 
4712 /* ----------------------------------------------------------------------------
4713  -- RCM Register Masks
4714  ---------------------------------------------------------------------------- */
4715 
4716 /*!
4717  * @addtogroup RCM_Register_Masks RCM Register Masks
4718  * @{
4719  */
4720 
4721 /* SRS0 Bit Fields */
4722 #define RCM_SRS0_WAKEUP_MASK 0x1u
4723 #define RCM_SRS0_WAKEUP_SHIFT 0
4724 #define RCM_SRS0_WAKEUP_WIDTH 1
4725 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
4726 #define RCM_SRS0_LVD_MASK 0x2u
4727 #define RCM_SRS0_LVD_SHIFT 1
4728 #define RCM_SRS0_LVD_WIDTH 1
4729 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
4730 #define RCM_SRS0_LOC_MASK 0x4u
4731 #define RCM_SRS0_LOC_SHIFT 2
4732 #define RCM_SRS0_LOC_WIDTH 1
4733 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
4734 #define RCM_SRS0_LOL_MASK 0x8u
4735 #define RCM_SRS0_LOL_SHIFT 3
4736 #define RCM_SRS0_LOL_WIDTH 1
4737 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
4738 #define RCM_SRS0_WDOG_MASK 0x20u
4739 #define RCM_SRS0_WDOG_SHIFT 5
4740 #define RCM_SRS0_WDOG_WIDTH 1
4741 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
4742 #define RCM_SRS0_PIN_MASK 0x40u
4743 #define RCM_SRS0_PIN_SHIFT 6
4744 #define RCM_SRS0_PIN_WIDTH 1
4745 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
4746 #define RCM_SRS0_POR_MASK 0x80u
4747 #define RCM_SRS0_POR_SHIFT 7
4748 #define RCM_SRS0_POR_WIDTH 1
4749 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
4750 /* SRS1 Bit Fields */
4751 #define RCM_SRS1_LOCKUP_MASK 0x2u
4752 #define RCM_SRS1_LOCKUP_SHIFT 1
4753 #define RCM_SRS1_LOCKUP_WIDTH 1
4754 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
4755 #define RCM_SRS1_SW_MASK 0x4u
4756 #define RCM_SRS1_SW_SHIFT 2
4757 #define RCM_SRS1_SW_WIDTH 1
4758 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
4759 #define RCM_SRS1_MDM_AP_MASK 0x8u
4760 #define RCM_SRS1_MDM_AP_SHIFT 3
4761 #define RCM_SRS1_MDM_AP_WIDTH 1
4762 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
4763 #define RCM_SRS1_SACKERR_MASK 0x20u
4764 #define RCM_SRS1_SACKERR_SHIFT 5
4765 #define RCM_SRS1_SACKERR_WIDTH 1
4766 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
4767 /* RPFC Bit Fields */
4768 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
4769 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
4770 #define RCM_RPFC_RSTFLTSRW_WIDTH 2
4771 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
4772 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
4773 #define RCM_RPFC_RSTFLTSS_SHIFT 2
4774 #define RCM_RPFC_RSTFLTSS_WIDTH 1
4775 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
4776 /* RPFW Bit Fields */
4777 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
4778 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
4779 #define RCM_RPFW_RSTFLTSEL_WIDTH 5
4780 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
4781 
4782 /*!
4783  * @}
4784  */ /* end of group RCM_Register_Masks */
4785 
4786 
4787 /* RCM - Peripheral instance base addresses */
4788 /** Peripheral RCM base address */
4789 #define RCM_BASE (0x4007F000u)
4790 /** Peripheral RCM base pointer */
4791 #define RCM ((RCM_Type *)RCM_BASE)
4792 #define RCM_BASE_PTR (RCM)
4793 /** Array initializer of RCM peripheral base addresses */
4794 #define RCM_BASE_ADDRS { RCM_BASE }
4795 /** Array initializer of RCM peripheral base pointers */
4796 #define RCM_BASE_PTRS { RCM }
4797 
4798 /* ----------------------------------------------------------------------------
4799  -- RCM - Register accessor macros
4800  ---------------------------------------------------------------------------- */
4801 
4802 /*!
4803  * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
4804  * @{
4805  */
4806 
4807 
4808 /* RCM - Register instance definitions */
4809 /* RCM */
4810 #define RCM_SRS0 RCM_SRS0_REG(RCM)
4811 #define RCM_SRS1 RCM_SRS1_REG(RCM)
4812 #define RCM_RPFC RCM_RPFC_REG(RCM)
4813 #define RCM_RPFW RCM_RPFW_REG(RCM)
4814 
4815 /*!
4816  * @}
4817  */ /* end of group RCM_Register_Accessor_Macros */
4818 
4819 
4820 /*!
4821  * @}
4822  */ /* end of group RCM_Peripheral_Access_Layer */
4823 
4824 
4825 /* ----------------------------------------------------------------------------
4826  -- ROM Peripheral Access Layer
4827  ---------------------------------------------------------------------------- */
4828 
4829 /*!
4830  * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
4831  * @{
4832  */
4833 
4834 /** ROM - Register Layout Typedef */
4835 typedef struct {
4836  __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
4837  __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
4838  uint8_t RESERVED_0[4028];
4839  __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
4840  __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
4841  __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
4842  __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
4843  __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
4844  __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
4845  __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
4846  __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
4847  __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
4848  __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
4849 } ROM_Type, *ROM_MemMapPtr;
4850 
4851 /* ----------------------------------------------------------------------------
4852  -- ROM - Register accessor macros
4853  ---------------------------------------------------------------------------- */
4854 
4855 /*!
4856  * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
4857  * @{
4858  */
4859 
4860 
4861 /* ROM - Register accessors */
4862 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
4863 #define ROM_ENTRY_COUNT 3
4864 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
4865 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
4866 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
4867 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
4868 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
4869 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
4870 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
4871 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
4872 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
4873 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
4874 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
4875 #define ROM_COMPID_COUNT 4
4876 
4877 /*!
4878  * @}
4879  */ /* end of group ROM_Register_Accessor_Macros */
4880 
4881 
4882 /* ----------------------------------------------------------------------------
4883  -- ROM Register Masks
4884  ---------------------------------------------------------------------------- */
4885 
4886 /*!
4887  * @addtogroup ROM_Register_Masks ROM Register Masks
4888  * @{
4889  */
4890 
4891 /* ENTRY Bit Fields */
4892 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
4893 #define ROM_ENTRY_ENTRY_SHIFT 0
4894 #define ROM_ENTRY_ENTRY_WIDTH 32
4895 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
4896 /* TABLEMARK Bit Fields */
4897 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
4898 #define ROM_TABLEMARK_MARK_SHIFT 0
4899 #define ROM_TABLEMARK_MARK_WIDTH 32
4900 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
4901 /* SYSACCESS Bit Fields */
4902 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
4903 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
4904 #define ROM_SYSACCESS_SYSACCESS_WIDTH 32
4905 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
4906 /* PERIPHID4 Bit Fields */
4907 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
4908 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
4909 #define ROM_PERIPHID4_PERIPHID_WIDTH 32
4910 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
4911 /* PERIPHID5 Bit Fields */
4912 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
4913 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
4914 #define ROM_PERIPHID5_PERIPHID_WIDTH 32
4915 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
4916 /* PERIPHID6 Bit Fields */
4917 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
4918 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
4919 #define ROM_PERIPHID6_PERIPHID_WIDTH 32
4920 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
4921 /* PERIPHID7 Bit Fields */
4922 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
4923 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
4924 #define ROM_PERIPHID7_PERIPHID_WIDTH 32
4925 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
4926 /* PERIPHID0 Bit Fields */
4927 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
4928 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
4929 #define ROM_PERIPHID0_PERIPHID_WIDTH 32
4930 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
4931 /* PERIPHID1 Bit Fields */
4932 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
4933 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
4934 #define ROM_PERIPHID1_PERIPHID_WIDTH 32
4935 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
4936 /* PERIPHID2 Bit Fields */
4937 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
4938 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
4939 #define ROM_PERIPHID2_PERIPHID_WIDTH 32
4940 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
4941 /* PERIPHID3 Bit Fields */
4942 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
4943 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
4944 #define ROM_PERIPHID3_PERIPHID_WIDTH 32
4945 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
4946 /* COMPID Bit Fields */
4947 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
4948 #define ROM_COMPID_COMPID_SHIFT 0
4949 #define ROM_COMPID_COMPID_WIDTH 32
4950 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
4951 
4952 /*!
4953  * @}
4954  */ /* end of group ROM_Register_Masks */
4955 
4956 
4957 /* ROM - Peripheral instance base addresses */
4958 /** Peripheral ROM base address */
4959 #define ROM_BASE (0xF0002000u)
4960 /** Peripheral ROM base pointer */
4961 #define ROM ((ROM_Type *)ROM_BASE)
4962 #define ROM_BASE_PTR (ROM)
4963 /** Array initializer of ROM peripheral base addresses */
4964 #define ROM_BASE_ADDRS { ROM_BASE }
4965 /** Array initializer of ROM peripheral base pointers */
4966 #define ROM_BASE_PTRS { ROM }
4967 
4968 /* ----------------------------------------------------------------------------
4969  -- ROM - Register accessor macros
4970  ---------------------------------------------------------------------------- */
4971 
4972 /*!
4973  * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
4974  * @{
4975  */
4976 
4977 
4978 /* ROM - Register instance definitions */
4979 /* ROM */
4980 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
4981 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
4982 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
4983 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
4984 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
4985 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
4986 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
4987 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
4988 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
4989 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
4990 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
4991 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
4992 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
4993 #define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
4994 #define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
4995 #define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
4996 #define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
4997 
4998 /* ROM - Register array accessors */
4999 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
5000 #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
5001 
5002 /*!
5003  * @}
5004  */ /* end of group ROM_Register_Accessor_Macros */
5005 
5006 
5007 /*!
5008  * @}
5009  */ /* end of group ROM_Peripheral_Access_Layer */
5010 
5011 
5012 /* ----------------------------------------------------------------------------
5013  -- RTC Peripheral Access Layer
5014  ---------------------------------------------------------------------------- */
5015 
5016 /*!
5017  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
5018  * @{
5019  */
5020 
5021 /** RTC - Register Layout Typedef */
5022 typedef struct {
5023  __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
5024  __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
5025  __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
5026  __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
5027  __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
5028  __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
5029  __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
5030  __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
5031 } RTC_Type, *RTC_MemMapPtr;
5032 
5033 /* ----------------------------------------------------------------------------
5034  -- RTC - Register accessor macros
5035  ---------------------------------------------------------------------------- */
5036 
5037 /*!
5038  * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
5039  * @{
5040  */
5041 
5042 
5043 /* RTC - Register accessors */
5044 #define RTC_TSR_REG(base) ((base)->TSR)
5045 #define RTC_TPR_REG(base) ((base)->TPR)
5046 #define RTC_TAR_REG(base) ((base)->TAR)
5047 #define RTC_TCR_REG(base) ((base)->TCR)
5048 #define RTC_CR_REG(base) ((base)->CR)
5049 #define RTC_SR_REG(base) ((base)->SR)
5050 #define RTC_LR_REG(base) ((base)->LR)
5051 #define RTC_IER_REG(base) ((base)->IER)
5052 
5053 /*!
5054  * @}
5055  */ /* end of group RTC_Register_Accessor_Macros */
5056 
5057 
5058 /* ----------------------------------------------------------------------------
5059  -- RTC Register Masks
5060  ---------------------------------------------------------------------------- */
5061 
5062 /*!
5063  * @addtogroup RTC_Register_Masks RTC Register Masks
5064  * @{
5065  */
5066 
5067 /* TSR Bit Fields */
5068 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
5069 #define RTC_TSR_TSR_SHIFT 0
5070 #define RTC_TSR_TSR_WIDTH 32
5071 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
5072 /* TPR Bit Fields */
5073 #define RTC_TPR_TPR_MASK 0xFFFFu
5074 #define RTC_TPR_TPR_SHIFT 0
5075 #define RTC_TPR_TPR_WIDTH 16
5076 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
5077 /* TAR Bit Fields */
5078 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
5079 #define RTC_TAR_TAR_SHIFT 0
5080 #define RTC_TAR_TAR_WIDTH 32
5081 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
5082 /* TCR Bit Fields */
5083 #define RTC_TCR_TCR_MASK 0xFFu
5084 #define RTC_TCR_TCR_SHIFT 0
5085 #define RTC_TCR_TCR_WIDTH 8
5086 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
5087 #define RTC_TCR_CIR_MASK 0xFF00u
5088 #define RTC_TCR_CIR_SHIFT 8
5089 #define RTC_TCR_CIR_WIDTH 8
5090 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
5091 #define RTC_TCR_TCV_MASK 0xFF0000u
5092 #define RTC_TCR_TCV_SHIFT 16
5093 #define RTC_TCR_TCV_WIDTH 8
5094 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
5095 #define RTC_TCR_CIC_MASK 0xFF000000u
5096 #define RTC_TCR_CIC_SHIFT 24
5097 #define RTC_TCR_CIC_WIDTH 8
5098 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
5099 /* CR Bit Fields */
5100 #define RTC_CR_SWR_MASK 0x1u
5101 #define RTC_CR_SWR_SHIFT 0
5102 #define RTC_CR_SWR_WIDTH 1
5103 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
5104 #define RTC_CR_WPE_MASK 0x2u
5105 #define RTC_CR_WPE_SHIFT 1
5106 #define RTC_CR_WPE_WIDTH 1
5107 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
5108 #define RTC_CR_SUP_MASK 0x4u
5109 #define RTC_CR_SUP_SHIFT 2
5110 #define RTC_CR_SUP_WIDTH 1
5111 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
5112 #define RTC_CR_UM_MASK 0x8u
5113 #define RTC_CR_UM_SHIFT 3
5114 #define RTC_CR_UM_WIDTH 1
5115 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
5116 #define RTC_CR_OSCE_MASK 0x100u
5117 #define RTC_CR_OSCE_SHIFT 8
5118 #define RTC_CR_OSCE_WIDTH 1
5119 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
5120 #define RTC_CR_CLKO_MASK 0x200u
5121 #define RTC_CR_CLKO_SHIFT 9
5122 #define RTC_CR_CLKO_WIDTH 1
5123 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
5124 #define RTC_CR_SC16P_MASK 0x400u
5125 #define RTC_CR_SC16P_SHIFT 10
5126 #define RTC_CR_SC16P_WIDTH 1
5127 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
5128 #define RTC_CR_SC8P_MASK 0x800u
5129 #define RTC_CR_SC8P_SHIFT 11
5130 #define RTC_CR_SC8P_WIDTH 1
5131 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
5132 #define RTC_CR_SC4P_MASK 0x1000u
5133 #define RTC_CR_SC4P_SHIFT 12
5134 #define RTC_CR_SC4P_WIDTH 1
5135 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
5136 #define RTC_CR_SC2P_MASK 0x2000u
5137 #define RTC_CR_SC2P_SHIFT 13
5138 #define RTC_CR_SC2P_WIDTH 1
5139 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
5140 /* SR Bit Fields */
5141 #define RTC_SR_TIF_MASK 0x1u
5142 #define RTC_SR_TIF_SHIFT 0
5143 #define RTC_SR_TIF_WIDTH 1
5144 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
5145 #define RTC_SR_TOF_MASK 0x2u
5146 #define RTC_SR_TOF_SHIFT 1
5147 #define RTC_SR_TOF_WIDTH 1
5148 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
5149 #define RTC_SR_TAF_MASK 0x4u
5150 #define RTC_SR_TAF_SHIFT 2
5151 #define RTC_SR_TAF_WIDTH 1
5152 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
5153 #define RTC_SR_TCE_MASK 0x10u
5154 #define RTC_SR_TCE_SHIFT 4
5155 #define RTC_SR_TCE_WIDTH 1
5156 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
5157 /* LR Bit Fields */
5158 #define RTC_LR_TCL_MASK 0x8u
5159 #define RTC_LR_TCL_SHIFT 3
5160 #define RTC_LR_TCL_WIDTH 1
5161 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
5162 #define RTC_LR_CRL_MASK 0x10u
5163 #define RTC_LR_CRL_SHIFT 4
5164 #define RTC_LR_CRL_WIDTH 1
5165 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
5166 #define RTC_LR_SRL_MASK 0x20u
5167 #define RTC_LR_SRL_SHIFT 5
5168 #define RTC_LR_SRL_WIDTH 1
5169 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
5170 #define RTC_LR_LRL_MASK 0x40u
5171 #define RTC_LR_LRL_SHIFT 6
5172 #define RTC_LR_LRL_WIDTH 1
5173 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
5174 /* IER Bit Fields */
5175 #define RTC_IER_TIIE_MASK 0x1u
5176 #define RTC_IER_TIIE_SHIFT 0
5177 #define RTC_IER_TIIE_WIDTH 1
5178 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
5179 #define RTC_IER_TOIE_MASK 0x2u
5180 #define RTC_IER_TOIE_SHIFT 1
5181 #define RTC_IER_TOIE_WIDTH 1
5182 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
5183 #define RTC_IER_TAIE_MASK 0x4u
5184 #define RTC_IER_TAIE_SHIFT 2
5185 #define RTC_IER_TAIE_WIDTH 1
5186 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
5187 #define RTC_IER_TSIE_MASK 0x10u
5188 #define RTC_IER_TSIE_SHIFT 4
5189 #define RTC_IER_TSIE_WIDTH 1
5190 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
5191 #define RTC_IER_WPON_MASK 0x80u
5192 #define RTC_IER_WPON_SHIFT 7
5193 #define RTC_IER_WPON_WIDTH 1
5194 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
5195 
5196 /*!
5197  * @}
5198  */ /* end of group RTC_Register_Masks */
5199 
5200 
5201 /* RTC - Peripheral instance base addresses */
5202 /** Peripheral RTC base address */
5203 #define RTC_BASE (0x4003D000u)
5204 /** Peripheral RTC base pointer */
5205 #define RTC ((RTC_Type *)RTC_BASE)
5206 #define RTC_BASE_PTR (RTC)
5207 /** Array initializer of RTC peripheral base addresses */
5208 #define RTC_BASE_ADDRS { RTC_BASE }
5209 /** Array initializer of RTC peripheral base pointers */
5210 #define RTC_BASE_PTRS { RTC }
5211 /** Interrupt vectors for the RTC peripheral type */
5212 #define RTC_IRQS { RTC_IRQn }
5213 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
5214 
5215 /* ----------------------------------------------------------------------------
5216  -- RTC - Register accessor macros
5217  ---------------------------------------------------------------------------- */
5218 
5219 /*!
5220  * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
5221  * @{
5222  */
5223 
5224 
5225 /* RTC - Register instance definitions */
5226 /* RTC */
5227 #define RTC_TSR RTC_TSR_REG(RTC)
5228 #define RTC_TPR RTC_TPR_REG(RTC)
5229 #define RTC_TAR RTC_TAR_REG(RTC)
5230 #define RTC_TCR RTC_TCR_REG(RTC)
5231 #define RTC_CR RTC_CR_REG(RTC)
5232 #define RTC_SR RTC_SR_REG(RTC)
5233 #define RTC_LR RTC_LR_REG(RTC)
5234 #define RTC_IER RTC_IER_REG(RTC)
5235 
5236 /*!
5237  * @}
5238  */ /* end of group RTC_Register_Accessor_Macros */
5239 
5240 
5241 /*!
5242  * @}
5243  */ /* end of group RTC_Peripheral_Access_Layer */
5244 
5245 
5246 /* ----------------------------------------------------------------------------
5247  -- SIM Peripheral Access Layer
5248  ---------------------------------------------------------------------------- */
5249 
5250 /*!
5251  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
5252  * @{
5253  */
5254 
5255 /** SIM - Register Layout Typedef */
5256 typedef struct {
5257  __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
5258  __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
5259  uint8_t RESERVED_0[4092];
5260  __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
5261  uint8_t RESERVED_1[4];
5262  __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
5263  __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
5264  uint8_t RESERVED_2[4];
5265  __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
5266  uint8_t RESERVED_3[8];
5267  __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
5268  uint8_t RESERVED_4[12];
5269  __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
5270  __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
5271  __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
5272  __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
5273  __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
5274  uint8_t RESERVED_5[4];
5275  __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
5276  __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
5277  uint8_t RESERVED_6[4];
5278  __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
5279  __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
5280  __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
5281  uint8_t RESERVED_7[156];
5282  __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
5283  __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
5284 } SIM_Type, *SIM_MemMapPtr;
5285 
5286 /* ----------------------------------------------------------------------------
5287  -- SIM - Register accessor macros
5288  ---------------------------------------------------------------------------- */
5289 
5290 /*!
5291  * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
5292  * @{
5293  */
5294 
5295 
5296 /* SIM - Register accessors */
5297 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
5298 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
5299 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
5300 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
5301 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
5302 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
5303 #define SIM_SDID_REG(base) ((base)->SDID)
5304 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
5305 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
5306 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
5307 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
5308 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
5309 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
5310 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
5311 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
5312 #define SIM_UIDML_REG(base) ((base)->UIDML)
5313 #define SIM_UIDL_REG(base) ((base)->UIDL)
5314 #define SIM_COPC_REG(base) ((base)->COPC)
5315 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
5316 
5317 /*!
5318  * @}
5319  */ /* end of group SIM_Register_Accessor_Macros */
5320 
5321 
5322 /* ----------------------------------------------------------------------------
5323  -- SIM Register Masks
5324  ---------------------------------------------------------------------------- */
5325 
5326 /*!
5327  * @addtogroup SIM_Register_Masks SIM Register Masks
5328  * @{
5329  */
5330 
5331 /* SOPT1 Bit Fields */
5332 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
5333 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
5334 #define SIM_SOPT1_OSC32KSEL_WIDTH 2
5335 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
5336 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
5337 #define SIM_SOPT1_USBVSTBY_SHIFT 29
5338 #define SIM_SOPT1_USBVSTBY_WIDTH 1
5339 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
5340 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
5341 #define SIM_SOPT1_USBSSTBY_SHIFT 30
5342 #define SIM_SOPT1_USBSSTBY_WIDTH 1
5343 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
5344 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
5345 #define SIM_SOPT1_USBREGEN_SHIFT 31
5346 #define SIM_SOPT1_USBREGEN_WIDTH 1
5347 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
5348 /* SOPT1CFG Bit Fields */
5349 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
5350 #define SIM_SOPT1CFG_URWE_SHIFT 24
5351 #define SIM_SOPT1CFG_URWE_WIDTH 1
5352 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
5353 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
5354 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
5355 #define SIM_SOPT1CFG_UVSWE_WIDTH 1
5356 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
5357 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
5358 #define SIM_SOPT1CFG_USSWE_SHIFT 26
5359 #define SIM_SOPT1CFG_USSWE_WIDTH 1
5360 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
5361 /* SOPT2 Bit Fields */
5362 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
5363 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
5364 #define SIM_SOPT2_RTCCLKOUTSEL_WIDTH 1
5365 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
5366 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
5367 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
5368 #define SIM_SOPT2_CLKOUTSEL_WIDTH 3
5369 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
5370 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
5371 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
5372 #define SIM_SOPT2_PLLFLLSEL_WIDTH 1
5373 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
5374 #define SIM_SOPT2_USBSRC_MASK 0x40000u
5375 #define SIM_SOPT2_USBSRC_SHIFT 18
5376 #define SIM_SOPT2_USBSRC_WIDTH 1
5377 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
5378 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
5379 #define SIM_SOPT2_TPMSRC_SHIFT 24
5380 #define SIM_SOPT2_TPMSRC_WIDTH 2
5381 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
5382 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
5383 #define SIM_SOPT2_UART0SRC_SHIFT 26
5384 #define SIM_SOPT2_UART0SRC_WIDTH 2
5385 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
5386 /* SOPT4 Bit Fields */
5387 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
5388 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
5389 #define SIM_SOPT4_TPM1CH0SRC_WIDTH 1
5390 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
5391 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
5392 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
5393 #define SIM_SOPT4_TPM2CH0SRC_WIDTH 1
5394 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM2CH0SRC_SHIFT))&SIM_SOPT4_TPM2CH0SRC_MASK)
5395 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
5396 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
5397 #define SIM_SOPT4_TPM0CLKSEL_WIDTH 1
5398 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM0CLKSEL_SHIFT))&SIM_SOPT4_TPM0CLKSEL_MASK)
5399 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
5400 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
5401 #define SIM_SOPT4_TPM1CLKSEL_WIDTH 1
5402 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CLKSEL_SHIFT))&SIM_SOPT4_TPM1CLKSEL_MASK)
5403 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
5404 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
5405 #define SIM_SOPT4_TPM2CLKSEL_WIDTH 1
5406 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM2CLKSEL_SHIFT))&SIM_SOPT4_TPM2CLKSEL_MASK)
5407 /* SOPT5 Bit Fields */
5408 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
5409 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
5410 #define SIM_SOPT5_UART0TXSRC_WIDTH 2
5411 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
5412 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
5413 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
5414 #define SIM_SOPT5_UART0RXSRC_WIDTH 1
5415 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
5416 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
5417 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
5418 #define SIM_SOPT5_UART1TXSRC_WIDTH 2
5419 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
5420 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
5421 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
5422 #define SIM_SOPT5_UART1RXSRC_WIDTH 1
5423 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
5424 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
5425 #define SIM_SOPT5_UART0ODE_SHIFT 16
5426 #define SIM_SOPT5_UART0ODE_WIDTH 1
5427 #define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0ODE_SHIFT))&SIM_SOPT5_UART0ODE_MASK)
5428 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
5429 #define SIM_SOPT5_UART1ODE_SHIFT 17
5430 #define SIM_SOPT5_UART1ODE_WIDTH 1
5431 #define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1ODE_SHIFT))&SIM_SOPT5_UART1ODE_MASK)
5432 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
5433 #define SIM_SOPT5_UART2ODE_SHIFT 18
5434 #define SIM_SOPT5_UART2ODE_WIDTH 1
5435 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART2ODE_SHIFT))&SIM_SOPT5_UART2ODE_MASK)
5436 /* SOPT7 Bit Fields */
5437 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
5438 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
5439 #define SIM_SOPT7_ADC0TRGSEL_WIDTH 4
5440 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
5441 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
5442 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
5443 #define SIM_SOPT7_ADC0PRETRGSEL_WIDTH 1
5444 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
5445 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
5446 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
5447 #define SIM_SOPT7_ADC0ALTTRGEN_WIDTH 1
5448 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
5449 /* SDID Bit Fields */
5450 #define SIM_SDID_PINID_MASK 0xFu
5451 #define SIM_SDID_PINID_SHIFT 0
5452 #define SIM_SDID_PINID_WIDTH 4
5453 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
5454 #define SIM_SDID_DIEID_MASK 0xF80u
5455 #define SIM_SDID_DIEID_SHIFT 7
5456 #define SIM_SDID_DIEID_WIDTH 5
5457 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
5458 #define SIM_SDID_REVID_MASK 0xF000u
5459 #define SIM_SDID_REVID_SHIFT 12
5460 #define SIM_SDID_REVID_WIDTH 4
5461 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
5462 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
5463 #define SIM_SDID_SRAMSIZE_SHIFT 16
5464 #define SIM_SDID_SRAMSIZE_WIDTH 4
5465 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
5466 #define SIM_SDID_SERIESID_MASK 0xF00000u
5467 #define SIM_SDID_SERIESID_SHIFT 20
5468 #define SIM_SDID_SERIESID_WIDTH 4
5469 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
5470 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
5471 #define SIM_SDID_SUBFAMID_SHIFT 24
5472 #define SIM_SDID_SUBFAMID_WIDTH 4
5473 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
5474 #define SIM_SDID_FAMID_MASK 0xF0000000u
5475 #define SIM_SDID_FAMID_SHIFT 28
5476 #define SIM_SDID_FAMID_WIDTH 4
5477 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
5478 /* SCGC4 Bit Fields */
5479 #define SIM_SCGC4_I2C0_MASK 0x40u
5480 #define SIM_SCGC4_I2C0_SHIFT 6
5481 #define SIM_SCGC4_I2C0_WIDTH 1
5482 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
5483 #define SIM_SCGC4_I2C1_MASK 0x80u
5484 #define SIM_SCGC4_I2C1_SHIFT 7
5485 #define SIM_SCGC4_I2C1_WIDTH 1
5486 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
5487 #define SIM_SCGC4_UART0_MASK 0x400u
5488 #define SIM_SCGC4_UART0_SHIFT 10
5489 #define SIM_SCGC4_UART0_WIDTH 1
5490 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
5491 #define SIM_SCGC4_UART1_MASK 0x800u
5492 #define SIM_SCGC4_UART1_SHIFT 11
5493 #define SIM_SCGC4_UART1_WIDTH 1
5494 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
5495 #define SIM_SCGC4_UART2_MASK 0x1000u
5496 #define SIM_SCGC4_UART2_SHIFT 12
5497 #define SIM_SCGC4_UART2_WIDTH 1
5498 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
5499 #define SIM_SCGC4_USBOTG_MASK 0x40000u
5500 #define SIM_SCGC4_USBOTG_SHIFT 18
5501 #define SIM_SCGC4_USBOTG_WIDTH 1
5502 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
5503 #define SIM_SCGC4_CMP_MASK 0x80000u
5504 #define SIM_SCGC4_CMP_SHIFT 19
5505 #define SIM_SCGC4_CMP_WIDTH 1
5506 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
5507 #define SIM_SCGC4_SPI0_MASK 0x400000u
5508 #define SIM_SCGC4_SPI0_SHIFT 22
5509 #define SIM_SCGC4_SPI0_WIDTH 1
5510 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_SPI0_SHIFT))&SIM_SCGC4_SPI0_MASK)
5511 #define SIM_SCGC4_SPI1_MASK 0x800000u
5512 #define SIM_SCGC4_SPI1_SHIFT 23
5513 #define SIM_SCGC4_SPI1_WIDTH 1
5514 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_SPI1_SHIFT))&SIM_SCGC4_SPI1_MASK)
5515 /* SCGC5 Bit Fields */
5516 #define SIM_SCGC5_LPTMR_MASK 0x1u
5517 #define SIM_SCGC5_LPTMR_SHIFT 0
5518 #define SIM_SCGC5_LPTMR_WIDTH 1
5519 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
5520 #define SIM_SCGC5_TSI_MASK 0x20u
5521 #define SIM_SCGC5_TSI_SHIFT 5
5522 #define SIM_SCGC5_TSI_WIDTH 1
5523 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_TSI_SHIFT))&SIM_SCGC5_TSI_MASK)
5524 #define SIM_SCGC5_PORTA_MASK 0x200u
5525 #define SIM_SCGC5_PORTA_SHIFT 9
5526 #define SIM_SCGC5_PORTA_WIDTH 1
5527 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
5528 #define SIM_SCGC5_PORTB_MASK 0x400u
5529 #define SIM_SCGC5_PORTB_SHIFT 10
5530 #define SIM_SCGC5_PORTB_WIDTH 1
5531 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
5532 #define SIM_SCGC5_PORTC_MASK 0x800u
5533 #define SIM_SCGC5_PORTC_SHIFT 11
5534 #define SIM_SCGC5_PORTC_WIDTH 1
5535 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
5536 #define SIM_SCGC5_PORTD_MASK 0x1000u
5537 #define SIM_SCGC5_PORTD_SHIFT 12
5538 #define SIM_SCGC5_PORTD_WIDTH 1
5539 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
5540 #define SIM_SCGC5_PORTE_MASK 0x2000u
5541 #define SIM_SCGC5_PORTE_SHIFT 13
5542 #define SIM_SCGC5_PORTE_WIDTH 1
5543 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
5544 /* SCGC6 Bit Fields */
5545 #define SIM_SCGC6_FTF_MASK 0x1u
5546 #define SIM_SCGC6_FTF_SHIFT 0
5547 #define SIM_SCGC6_FTF_WIDTH 1
5548 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
5549 #define SIM_SCGC6_DMAMUX_MASK 0x2u
5550 #define SIM_SCGC6_DMAMUX_SHIFT 1
5551 #define SIM_SCGC6_DMAMUX_WIDTH 1
5552 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
5553 #define SIM_SCGC6_PIT_MASK 0x800000u
5554 #define SIM_SCGC6_PIT_SHIFT 23
5555 #define SIM_SCGC6_PIT_WIDTH 1
5556 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
5557 #define SIM_SCGC6_TPM0_MASK 0x1000000u
5558 #define SIM_SCGC6_TPM0_SHIFT 24
5559 #define SIM_SCGC6_TPM0_WIDTH 1
5560 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
5561 #define SIM_SCGC6_TPM1_MASK 0x2000000u
5562 #define SIM_SCGC6_TPM1_SHIFT 25
5563 #define SIM_SCGC6_TPM1_WIDTH 1
5564 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
5565 #define SIM_SCGC6_TPM2_MASK 0x4000000u
5566 #define SIM_SCGC6_TPM2_SHIFT 26
5567 #define SIM_SCGC6_TPM2_WIDTH 1
5568 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM2_SHIFT))&SIM_SCGC6_TPM2_MASK)
5569 #define SIM_SCGC6_ADC0_MASK 0x8000000u
5570 #define SIM_SCGC6_ADC0_SHIFT 27
5571 #define SIM_SCGC6_ADC0_WIDTH 1
5572 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
5573 #define SIM_SCGC6_RTC_MASK 0x20000000u
5574 #define SIM_SCGC6_RTC_SHIFT 29
5575 #define SIM_SCGC6_RTC_WIDTH 1
5576 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
5577 #define SIM_SCGC6_DAC0_MASK 0x80000000u
5578 #define SIM_SCGC6_DAC0_SHIFT 31
5579 #define SIM_SCGC6_DAC0_WIDTH 1
5580 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
5581 /* SCGC7 Bit Fields */
5582 #define SIM_SCGC7_DMA_MASK 0x100u
5583 #define SIM_SCGC7_DMA_SHIFT 8
5584 #define SIM_SCGC7_DMA_WIDTH 1
5585 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
5586 /* CLKDIV1 Bit Fields */
5587 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
5588 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
5589 #define SIM_CLKDIV1_OUTDIV4_WIDTH 3
5590 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
5591 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
5592 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
5593 #define SIM_CLKDIV1_OUTDIV1_WIDTH 4
5594 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
5595 /* FCFG1 Bit Fields */
5596 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
5597 #define SIM_FCFG1_FLASHDIS_SHIFT 0
5598 #define SIM_FCFG1_FLASHDIS_WIDTH 1
5599 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
5600 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
5601 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
5602 #define SIM_FCFG1_FLASHDOZE_WIDTH 1
5603 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
5604 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
5605 #define SIM_FCFG1_PFSIZE_SHIFT 24
5606 #define SIM_FCFG1_PFSIZE_WIDTH 4
5607 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
5608 /* FCFG2 Bit Fields */
5609 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
5610 #define SIM_FCFG2_MAXADDR0_SHIFT 24
5611 #define SIM_FCFG2_MAXADDR0_WIDTH 7
5612 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
5613 /* UIDMH Bit Fields */
5614 #define SIM_UIDMH_UID_MASK 0xFFFFu
5615 #define SIM_UIDMH_UID_SHIFT 0
5616 #define SIM_UIDMH_UID_WIDTH 16
5617 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
5618 /* UIDML Bit Fields */
5619 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
5620 #define SIM_UIDML_UID_SHIFT 0
5621 #define SIM_UIDML_UID_WIDTH 32
5622 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
5623 /* UIDL Bit Fields */
5624 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
5625 #define SIM_UIDL_UID_SHIFT 0
5626 #define SIM_UIDL_UID_WIDTH 32
5627 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
5628 /* COPC Bit Fields */
5629 #define SIM_COPC_COPW_MASK 0x1u
5630 #define SIM_COPC_COPW_SHIFT 0
5631 #define SIM_COPC_COPW_WIDTH 1
5632 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPW_SHIFT))&SIM_COPC_COPW_MASK)
5633 #define SIM_COPC_COPCLKS_MASK 0x2u
5634 #define SIM_COPC_COPCLKS_SHIFT 1
5635 #define SIM_COPC_COPCLKS_WIDTH 1
5636 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKS_SHIFT))&SIM_COPC_COPCLKS_MASK)
5637 #define SIM_COPC_COPT_MASK 0xCu
5638 #define SIM_COPC_COPT_SHIFT 2
5639 #define SIM_COPC_COPT_WIDTH 2
5640 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
5641 /* SRVCOP Bit Fields */
5642 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
5643 #define SIM_SRVCOP_SRVCOP_SHIFT 0
5644 #define SIM_SRVCOP_SRVCOP_WIDTH 8
5645 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
5646 
5647 /*!
5648  * @}
5649  */ /* end of group SIM_Register_Masks */
5650 
5651 
5652 /* SIM - Peripheral instance base addresses */
5653 /** Peripheral SIM base address */
5654 #define SIM_BASE (0x40047000u)
5655 /** Peripheral SIM base pointer */
5656 #define SIM ((SIM_Type *)SIM_BASE)
5657 #define SIM_BASE_PTR (SIM)
5658 /** Array initializer of SIM peripheral base addresses */
5659 #define SIM_BASE_ADDRS { SIM_BASE }
5660 /** Array initializer of SIM peripheral base pointers */
5661 #define SIM_BASE_PTRS { SIM }
5662 
5663 /* ----------------------------------------------------------------------------
5664  -- SIM - Register accessor macros
5665  ---------------------------------------------------------------------------- */
5666 
5667 /*!
5668  * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
5669  * @{
5670  */
5671 
5672 
5673 /* SIM - Register instance definitions */
5674 /* SIM */
5675 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
5676 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
5677 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
5678 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
5679 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
5680 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
5681 #define SIM_SDID SIM_SDID_REG(SIM)
5682 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
5683 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
5684 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
5685 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
5686 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
5687 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
5688 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
5689 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
5690 #define SIM_UIDML SIM_UIDML_REG(SIM)
5691 #define SIM_UIDL SIM_UIDL_REG(SIM)
5692 #define SIM_COPC SIM_COPC_REG(SIM)
5693 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
5694 
5695 /*!
5696  * @}
5697  */ /* end of group SIM_Register_Accessor_Macros */
5698 
5699 
5700 /*!
5701  * @}
5702  */ /* end of group SIM_Peripheral_Access_Layer */
5703 
5704 
5705 /* ----------------------------------------------------------------------------
5706  -- SMC Peripheral Access Layer
5707  ---------------------------------------------------------------------------- */
5708 
5709 /*!
5710  * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
5711  * @{
5712  */
5713 
5714 /** SMC - Register Layout Typedef */
5715 typedef struct {
5716  __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
5717  __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
5718  __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
5719  __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
5720 } SMC_Type, *SMC_MemMapPtr;
5721 
5722 /* ----------------------------------------------------------------------------
5723  -- SMC - Register accessor macros
5724  ---------------------------------------------------------------------------- */
5725 
5726 /*!
5727  * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
5728  * @{
5729  */
5730 
5731 
5732 /* SMC - Register accessors */
5733 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
5734 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
5735 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
5736 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
5737 
5738 /*!
5739  * @}
5740  */ /* end of group SMC_Register_Accessor_Macros */
5741 
5742 
5743 /* ----------------------------------------------------------------------------
5744  -- SMC Register Masks
5745  ---------------------------------------------------------------------------- */
5746 
5747 /*!
5748  * @addtogroup SMC_Register_Masks SMC Register Masks
5749  * @{
5750  */
5751 
5752 /* PMPROT Bit Fields */
5753 #define SMC_PMPROT_AVLLS_MASK 0x2u
5754 #define SMC_PMPROT_AVLLS_SHIFT 1
5755 #define SMC_PMPROT_AVLLS_WIDTH 1
5756 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
5757 #define SMC_PMPROT_ALLS_MASK 0x8u
5758 #define SMC_PMPROT_ALLS_SHIFT 3
5759 #define SMC_PMPROT_ALLS_WIDTH 1
5760 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
5761 #define SMC_PMPROT_AVLP_MASK 0x20u
5762 #define SMC_PMPROT_AVLP_SHIFT 5
5763 #define SMC_PMPROT_AVLP_WIDTH 1
5764 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
5765 /* PMCTRL Bit Fields */
5766 #define SMC_PMCTRL_STOPM_MASK 0x7u
5767 #define SMC_PMCTRL_STOPM_SHIFT 0
5768 #define SMC_PMCTRL_STOPM_WIDTH 3
5769 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
5770 #define SMC_PMCTRL_STOPA_MASK 0x8u
5771 #define SMC_PMCTRL_STOPA_SHIFT 3
5772 #define SMC_PMCTRL_STOPA_WIDTH 1
5773 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
5774 #define SMC_PMCTRL_RUNM_MASK 0x60u
5775 #define SMC_PMCTRL_RUNM_SHIFT 5
5776 #define SMC_PMCTRL_RUNM_WIDTH 2
5777 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
5778 /* STOPCTRL Bit Fields */
5779 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
5780 #define SMC_STOPCTRL_VLLSM_SHIFT 0
5781 #define SMC_STOPCTRL_VLLSM_WIDTH 3
5782 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
5783 #define SMC_STOPCTRL_PORPO_MASK 0x20u
5784 #define SMC_STOPCTRL_PORPO_SHIFT 5
5785 #define SMC_STOPCTRL_PORPO_WIDTH 1
5786 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
5787 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
5788 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
5789 #define SMC_STOPCTRL_PSTOPO_WIDTH 2
5790 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
5791 /* PMSTAT Bit Fields */
5792 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
5793 #define SMC_PMSTAT_PMSTAT_SHIFT 0
5794 #define SMC_PMSTAT_PMSTAT_WIDTH 7
5795 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
5796 
5797 /*!
5798  * @}
5799  */ /* end of group SMC_Register_Masks */
5800 
5801 
5802 /* SMC - Peripheral instance base addresses */
5803 /** Peripheral SMC base address */
5804 #define SMC_BASE (0x4007E000u)
5805 /** Peripheral SMC base pointer */
5806 #define SMC ((SMC_Type *)SMC_BASE)
5807 #define SMC_BASE_PTR (SMC)
5808 /** Array initializer of SMC peripheral base addresses */
5809 #define SMC_BASE_ADDRS { SMC_BASE }
5810 /** Array initializer of SMC peripheral base pointers */
5811 #define SMC_BASE_PTRS { SMC }
5812 
5813 /* ----------------------------------------------------------------------------
5814  -- SMC - Register accessor macros
5815  ---------------------------------------------------------------------------- */
5816 
5817 /*!
5818  * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
5819  * @{
5820  */
5821 
5822 
5823 /* SMC - Register instance definitions */
5824 /* SMC */
5825 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
5826 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
5827 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
5828 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
5829 
5830 /*!
5831  * @}
5832  */ /* end of group SMC_Register_Accessor_Macros */
5833 
5834 
5835 /*!
5836  * @}
5837  */ /* end of group SMC_Peripheral_Access_Layer */
5838 
5839 
5840 /* ----------------------------------------------------------------------------
5841  -- SPI Peripheral Access Layer
5842  ---------------------------------------------------------------------------- */
5843 
5844 /*!
5845  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
5846  * @{
5847  */
5848 
5849 /** SPI - Register Layout Typedef */
5850 typedef struct {
5851  __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
5852  __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
5853  __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
5854  __IO uint8_t S; /**< SPI status register, offset: 0x3 */
5855  uint8_t RESERVED_0[1];
5856  __IO uint8_t D; /**< SPI data register, offset: 0x5 */
5857  uint8_t RESERVED_1[1];
5858  __IO uint8_t M; /**< SPI match register, offset: 0x7 */
5859 } SPI_Type, *SPI_MemMapPtr;
5860 
5861 /* ----------------------------------------------------------------------------
5862  -- SPI - Register accessor macros
5863  ---------------------------------------------------------------------------- */
5864 
5865 /*!
5866  * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
5867  * @{
5868  */
5869 
5870 
5871 /* SPI - Register accessors */
5872 #define SPI_C1_REG(base) ((base)->C1)
5873 #define SPI_C2_REG(base) ((base)->C2)
5874 #define SPI_BR_REG(base) ((base)->BR)
5875 #define SPI_S_REG(base) ((base)->S)
5876 #define SPI_D_REG(base) ((base)->D)
5877 #define SPI_M_REG(base) ((base)->M)
5878 
5879 /*!
5880  * @}
5881  */ /* end of group SPI_Register_Accessor_Macros */
5882 
5883 
5884 /* ----------------------------------------------------------------------------
5885  -- SPI Register Masks
5886  ---------------------------------------------------------------------------- */
5887 
5888 /*!
5889  * @addtogroup SPI_Register_Masks SPI Register Masks
5890  * @{
5891  */
5892 
5893 /* C1 Bit Fields */
5894 #define SPI_C1_LSBFE_MASK 0x1u
5895 #define SPI_C1_LSBFE_SHIFT 0
5896 #define SPI_C1_LSBFE_WIDTH 1
5897 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_LSBFE_SHIFT))&SPI_C1_LSBFE_MASK)
5898 #define SPI_C1_SSOE_MASK 0x2u
5899 #define SPI_C1_SSOE_SHIFT 1
5900 #define SPI_C1_SSOE_WIDTH 1
5901 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_SSOE_SHIFT))&SPI_C1_SSOE_MASK)
5902 #define SPI_C1_CPHA_MASK 0x4u
5903 #define SPI_C1_CPHA_SHIFT 2
5904 #define SPI_C1_CPHA_WIDTH 1
5905 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_CPHA_SHIFT))&SPI_C1_CPHA_MASK)
5906 #define SPI_C1_CPOL_MASK 0x8u
5907 #define SPI_C1_CPOL_SHIFT 3
5908 #define SPI_C1_CPOL_WIDTH 1
5909 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_CPOL_SHIFT))&SPI_C1_CPOL_MASK)
5910 #define SPI_C1_MSTR_MASK 0x10u
5911 #define SPI_C1_MSTR_SHIFT 4
5912 #define SPI_C1_MSTR_WIDTH 1
5913 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_MSTR_SHIFT))&SPI_C1_MSTR_MASK)
5914 #define SPI_C1_SPTIE_MASK 0x20u
5915 #define SPI_C1_SPTIE_SHIFT 5
5916 #define SPI_C1_SPTIE_WIDTH 1
5917 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPTIE_SHIFT))&SPI_C1_SPTIE_MASK)
5918 #define SPI_C1_SPE_MASK 0x40u
5919 #define SPI_C1_SPE_SHIFT 6
5920 #define SPI_C1_SPE_WIDTH 1
5921 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPE_SHIFT))&SPI_C1_SPE_MASK)
5922 #define SPI_C1_SPIE_MASK 0x80u
5923 #define SPI_C1_SPIE_SHIFT 7
5924 #define SPI_C1_SPIE_WIDTH 1
5925 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C1_SPIE_SHIFT))&SPI_C1_SPIE_MASK)
5926 /* C2 Bit Fields */
5927 #define SPI_C2_SPC0_MASK 0x1u
5928 #define SPI_C2_SPC0_SHIFT 0
5929 #define SPI_C2_SPC0_WIDTH 1
5930 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPC0_SHIFT))&SPI_C2_SPC0_MASK)
5931 #define SPI_C2_SPISWAI_MASK 0x2u
5932 #define SPI_C2_SPISWAI_SHIFT 1
5933 #define SPI_C2_SPISWAI_WIDTH 1
5934 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPISWAI_SHIFT))&SPI_C2_SPISWAI_MASK)
5935 #define SPI_C2_RXDMAE_MASK 0x4u
5936 #define SPI_C2_RXDMAE_SHIFT 2
5937 #define SPI_C2_RXDMAE_WIDTH 1
5938 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_RXDMAE_SHIFT))&SPI_C2_RXDMAE_MASK)
5939 #define SPI_C2_BIDIROE_MASK 0x8u
5940 #define SPI_C2_BIDIROE_SHIFT 3
5941 #define SPI_C2_BIDIROE_WIDTH 1
5942 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_BIDIROE_SHIFT))&SPI_C2_BIDIROE_MASK)
5943 #define SPI_C2_MODFEN_MASK 0x10u
5944 #define SPI_C2_MODFEN_SHIFT 4
5945 #define SPI_C2_MODFEN_WIDTH 1
5946 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_MODFEN_SHIFT))&SPI_C2_MODFEN_MASK)
5947 #define SPI_C2_TXDMAE_MASK 0x20u
5948 #define SPI_C2_TXDMAE_SHIFT 5
5949 #define SPI_C2_TXDMAE_WIDTH 1
5950 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_TXDMAE_SHIFT))&SPI_C2_TXDMAE_MASK)
5951 #define SPI_C2_SPMIE_MASK 0x80u
5952 #define SPI_C2_SPMIE_SHIFT 7
5953 #define SPI_C2_SPMIE_WIDTH 1
5954 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x))<<SPI_C2_SPMIE_SHIFT))&SPI_C2_SPMIE_MASK)
5955 /* BR Bit Fields */
5956 #define SPI_BR_SPR_MASK 0xFu
5957 #define SPI_BR_SPR_SHIFT 0
5958 #define SPI_BR_SPR_WIDTH 4
5959 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
5960 #define SPI_BR_SPPR_MASK 0x70u
5961 #define SPI_BR_SPPR_SHIFT 4
5962 #define SPI_BR_SPPR_WIDTH 3
5963 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
5964 /* S Bit Fields */
5965 #define SPI_S_MODF_MASK 0x10u
5966 #define SPI_S_MODF_SHIFT 4
5967 #define SPI_S_MODF_WIDTH 1
5968 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x))<<SPI_S_MODF_SHIFT))&SPI_S_MODF_MASK)
5969 #define SPI_S_SPTEF_MASK 0x20u
5970 #define SPI_S_SPTEF_SHIFT 5
5971 #define SPI_S_SPTEF_WIDTH 1
5972 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x))<<SPI_S_SPTEF_SHIFT))&SPI_S_SPTEF_MASK)
5973 #define SPI_S_SPMF_MASK 0x40u
5974 #define SPI_S_SPMF_SHIFT 6
5975 #define SPI_S_SPMF_WIDTH 1
5976 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x))<<SPI_S_SPMF_SHIFT))&SPI_S_SPMF_MASK)
5977 #define SPI_S_SPRF_MASK 0x80u
5978 #define SPI_S_SPRF_SHIFT 7
5979 #define SPI_S_SPRF_WIDTH 1
5980 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x))<<SPI_S_SPRF_SHIFT))&SPI_S_SPRF_MASK)
5981 /* D Bit Fields */
5982 #define SPI_D_Bits_MASK 0xFFu
5983 #define SPI_D_Bits_SHIFT 0
5984 #define SPI_D_Bits_WIDTH 8
5985 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
5986 /* M Bit Fields */
5987 #define SPI_M_Bits_MASK 0xFFu
5988 #define SPI_M_Bits_SHIFT 0
5989 #define SPI_M_Bits_WIDTH 8
5990 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
5991 
5992 /*!
5993  * @}
5994  */ /* end of group SPI_Register_Masks */
5995 
5996 
5997 /* SPI - Peripheral instance base addresses */
5998 /** Peripheral SPI0 base address */
5999 #define SPI0_BASE (0x40076000u)
6000 /** Peripheral SPI0 base pointer */
6001 #define SPI0 ((SPI_Type *)SPI0_BASE)
6002 #define SPI0_BASE_PTR (SPI0)
6003 /** Peripheral SPI1 base address */
6004 #define SPI1_BASE (0x40077000u)
6005 /** Peripheral SPI1 base pointer */
6006 #define SPI1 ((SPI_Type *)SPI1_BASE)
6007 #define SPI1_BASE_PTR (SPI1)
6008 /** Array initializer of SPI peripheral base addresses */
6009 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
6010 /** Array initializer of SPI peripheral base pointers */
6011 #define SPI_BASE_PTRS { SPI0, SPI1 }
6012 /** Interrupt vectors for the SPI peripheral type */
6013 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
6014 
6015 /* ----------------------------------------------------------------------------
6016  -- SPI - Register accessor macros
6017  ---------------------------------------------------------------------------- */
6018 
6019 /*!
6020  * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
6021  * @{
6022  */
6023 
6024 
6025 /* SPI - Register instance definitions */
6026 /* SPI0 */
6027 #define SPI0_C1 SPI_C1_REG(SPI0)
6028 #define SPI0_C2 SPI_C2_REG(SPI0)
6029 #define SPI0_BR SPI_BR_REG(SPI0)
6030 #define SPI0_S SPI_S_REG(SPI0)
6031 #define SPI0_D SPI_D_REG(SPI0)
6032 #define SPI0_M SPI_M_REG(SPI0)
6033 /* SPI1 */
6034 #define SPI1_C1 SPI_C1_REG(SPI1)
6035 #define SPI1_C2 SPI_C2_REG(SPI1)
6036 #define SPI1_BR SPI_BR_REG(SPI1)
6037 #define SPI1_S SPI_S_REG(SPI1)
6038 #define SPI1_D SPI_D_REG(SPI1)
6039 #define SPI1_M SPI_M_REG(SPI1)
6040 
6041 /*!
6042  * @}
6043  */ /* end of group SPI_Register_Accessor_Macros */
6044 
6045 
6046 /*!
6047  * @}
6048  */ /* end of group SPI_Peripheral_Access_Layer */
6049 
6050 
6051 /* ----------------------------------------------------------------------------
6052  -- TPM Peripheral Access Layer
6053  ---------------------------------------------------------------------------- */
6054 
6055 /*!
6056  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
6057  * @{
6058  */
6059 
6060 /** TPM - Register Layout Typedef */
6061 typedef struct {
6062  __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
6063  __IO uint32_t CNT; /**< Counter, offset: 0x4 */
6064  __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
6065  struct { /* offset: 0xC, array step: 0x8 */
6066  __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
6067  __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
6068  } CONTROLS[6];
6069  uint8_t RESERVED_0[20];
6070  __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
6071  uint8_t RESERVED_1[48];
6072  __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
6073 } TPM_Type, *TPM_MemMapPtr;
6074 
6075 /* ----------------------------------------------------------------------------
6076  -- TPM - Register accessor macros
6077  ---------------------------------------------------------------------------- */
6078 
6079 /*!
6080  * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
6081  * @{
6082  */
6083 
6084 
6085 /* TPM - Register accessors */
6086 #define TPM_SC_REG(base) ((base)->SC)
6087 #define TPM_CNT_REG(base) ((base)->CNT)
6088 #define TPM_MOD_REG(base) ((base)->MOD)
6089 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
6090 #define TPM_CnSC_COUNT 6
6091 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
6092 #define TPM_CnV_COUNT 6
6093 #define TPM_STATUS_REG(base) ((base)->STATUS)
6094 #define TPM_CONF_REG(base) ((base)->CONF)
6095 
6096 /*!
6097  * @}
6098  */ /* end of group TPM_Register_Accessor_Macros */
6099 
6100 
6101 /* ----------------------------------------------------------------------------
6102  -- TPM Register Masks
6103  ---------------------------------------------------------------------------- */
6104 
6105 /*!
6106  * @addtogroup TPM_Register_Masks TPM Register Masks
6107  * @{
6108  */
6109 
6110 /* SC Bit Fields */
6111 #define TPM_SC_PS_MASK 0x7u
6112 #define TPM_SC_PS_SHIFT 0
6113 #define TPM_SC_PS_WIDTH 3
6114 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
6115 #define TPM_SC_CMOD_MASK 0x18u
6116 #define TPM_SC_CMOD_SHIFT 3
6117 #define TPM_SC_CMOD_WIDTH 2
6118 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
6119 #define TPM_SC_CPWMS_MASK 0x20u
6120 #define TPM_SC_CPWMS_SHIFT 5
6121 #define TPM_SC_CPWMS_WIDTH 1
6122 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CPWMS_SHIFT))&TPM_SC_CPWMS_MASK)
6123 #define TPM_SC_TOIE_MASK 0x40u
6124 #define TPM_SC_TOIE_SHIFT 6
6125 #define TPM_SC_TOIE_WIDTH 1
6126 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOIE_SHIFT))&TPM_SC_TOIE_MASK)
6127 #define TPM_SC_TOF_MASK 0x80u
6128 #define TPM_SC_TOF_SHIFT 7
6129 #define TPM_SC_TOF_WIDTH 1
6130 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOF_SHIFT))&TPM_SC_TOF_MASK)
6131 #define TPM_SC_DMA_MASK 0x100u
6132 #define TPM_SC_DMA_SHIFT 8
6133 #define TPM_SC_DMA_WIDTH 1
6134 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_DMA_SHIFT))&TPM_SC_DMA_MASK)
6135 /* CNT Bit Fields */
6136 #define TPM_CNT_COUNT_MASK 0xFFFFu
6137 #define TPM_CNT_COUNT_SHIFT 0
6138 #define TPM_CNT_COUNT_WIDTH 16
6139 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
6140 /* MOD Bit Fields */
6141 #define TPM_MOD_MOD_MASK 0xFFFFu
6142 #define TPM_MOD_MOD_SHIFT 0
6143 #define TPM_MOD_MOD_WIDTH 16
6144 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
6145 /* CnSC Bit Fields */
6146 #define TPM_CnSC_DMA_MASK 0x1u
6147 #define TPM_CnSC_DMA_SHIFT 0
6148 #define TPM_CnSC_DMA_WIDTH 1
6149 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_DMA_SHIFT))&TPM_CnSC_DMA_MASK)
6150 #define TPM_CnSC_ELSA_MASK 0x4u
6151 #define TPM_CnSC_ELSA_SHIFT 2
6152 #define TPM_CnSC_ELSA_WIDTH 1
6153 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSA_SHIFT))&TPM_CnSC_ELSA_MASK)
6154 #define TPM_CnSC_ELSB_MASK 0x8u
6155 #define TPM_CnSC_ELSB_SHIFT 3
6156 #define TPM_CnSC_ELSB_WIDTH 1
6157 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSB_SHIFT))&TPM_CnSC_ELSB_MASK)
6158 #define TPM_CnSC_MSA_MASK 0x10u
6159 #define TPM_CnSC_MSA_SHIFT 4
6160 #define TPM_CnSC_MSA_WIDTH 1
6161 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSA_SHIFT))&TPM_CnSC_MSA_MASK)
6162 #define TPM_CnSC_MSB_MASK 0x20u
6163 #define TPM_CnSC_MSB_SHIFT 5
6164 #define TPM_CnSC_MSB_WIDTH 1
6165 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSB_SHIFT))&TPM_CnSC_MSB_MASK)
6166 #define TPM_CnSC_CHIE_MASK 0x40u
6167 #define TPM_CnSC_CHIE_SHIFT 6
6168 #define TPM_CnSC_CHIE_WIDTH 1
6169 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHIE_SHIFT))&TPM_CnSC_CHIE_MASK)
6170 #define TPM_CnSC_CHF_MASK 0x80u
6171 #define TPM_CnSC_CHF_SHIFT 7
6172 #define TPM_CnSC_CHF_WIDTH 1
6173 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHF_SHIFT))&TPM_CnSC_CHF_MASK)
6174 /* CnV Bit Fields */
6175 #define TPM_CnV_VAL_MASK 0xFFFFu
6176 #define TPM_CnV_VAL_SHIFT 0
6177 #define TPM_CnV_VAL_WIDTH 16
6178 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
6179 /* STATUS Bit Fields */
6180 #define TPM_STATUS_CH0F_MASK 0x1u
6181 #define TPM_STATUS_CH0F_SHIFT 0
6182 #define TPM_STATUS_CH0F_WIDTH 1
6183 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH0F_SHIFT))&TPM_STATUS_CH0F_MASK)
6184 #define TPM_STATUS_CH1F_MASK 0x2u
6185 #define TPM_STATUS_CH1F_SHIFT 1
6186 #define TPM_STATUS_CH1F_WIDTH 1
6187 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH1F_SHIFT))&TPM_STATUS_CH1F_MASK)
6188 #define TPM_STATUS_CH2F_MASK 0x4u
6189 #define TPM_STATUS_CH2F_SHIFT 2
6190 #define TPM_STATUS_CH2F_WIDTH 1
6191 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH2F_SHIFT))&TPM_STATUS_CH2F_MASK)
6192 #define TPM_STATUS_CH3F_MASK 0x8u
6193 #define TPM_STATUS_CH3F_SHIFT 3
6194 #define TPM_STATUS_CH3F_WIDTH 1
6195 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH3F_SHIFT))&TPM_STATUS_CH3F_MASK)
6196 #define TPM_STATUS_CH4F_MASK 0x10u
6197 #define TPM_STATUS_CH4F_SHIFT 4
6198 #define TPM_STATUS_CH4F_WIDTH 1
6199 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH4F_SHIFT))&TPM_STATUS_CH4F_MASK)
6200 #define TPM_STATUS_CH5F_MASK 0x20u
6201 #define TPM_STATUS_CH5F_SHIFT 5
6202 #define TPM_STATUS_CH5F_WIDTH 1
6203 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH5F_SHIFT))&TPM_STATUS_CH5F_MASK)
6204 #define TPM_STATUS_TOF_MASK 0x100u
6205 #define TPM_STATUS_TOF_SHIFT 8
6206 #define TPM_STATUS_TOF_WIDTH 1
6207 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_TOF_SHIFT))&TPM_STATUS_TOF_MASK)
6208 /* CONF Bit Fields */
6209 #define TPM_CONF_DOZEEN_MASK 0x20u
6210 #define TPM_CONF_DOZEEN_SHIFT 5
6211 #define TPM_CONF_DOZEEN_WIDTH 1
6212 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DOZEEN_SHIFT))&TPM_CONF_DOZEEN_MASK)
6213 #define TPM_CONF_DBGMODE_MASK 0xC0u
6214 #define TPM_CONF_DBGMODE_SHIFT 6
6215 #define TPM_CONF_DBGMODE_WIDTH 2
6216 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
6217 #define TPM_CONF_GTBEEN_MASK 0x200u
6218 #define TPM_CONF_GTBEEN_SHIFT 9
6219 #define TPM_CONF_GTBEEN_WIDTH 1
6220 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBEEN_SHIFT))&TPM_CONF_GTBEEN_MASK)
6221 #define TPM_CONF_CSOT_MASK 0x10000u
6222 #define TPM_CONF_CSOT_SHIFT 16
6223 #define TPM_CONF_CSOT_WIDTH 1
6224 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOT_SHIFT))&TPM_CONF_CSOT_MASK)
6225 #define TPM_CONF_CSOO_MASK 0x20000u
6226 #define TPM_CONF_CSOO_SHIFT 17
6227 #define TPM_CONF_CSOO_WIDTH 1
6228 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOO_SHIFT))&TPM_CONF_CSOO_MASK)
6229 #define TPM_CONF_CROT_MASK 0x40000u
6230 #define TPM_CONF_CROT_SHIFT 18
6231 #define TPM_CONF_CROT_WIDTH 1
6232 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CROT_SHIFT))&TPM_CONF_CROT_MASK)
6233 #define TPM_CONF_TRGSEL_MASK 0xF000000u
6234 #define TPM_CONF_TRGSEL_SHIFT 24
6235 #define TPM_CONF_TRGSEL_WIDTH 4
6236 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
6237 
6238 /*!
6239  * @}
6240  */ /* end of group TPM_Register_Masks */
6241 
6242 
6243 /* TPM - Peripheral instance base addresses */
6244 /** Peripheral TPM0 base address */
6245 #define TPM0_BASE (0x40038000u)
6246 /** Peripheral TPM0 base pointer */
6247 #define TPM0 ((TPM_Type *)TPM0_BASE)
6248 #define TPM0_BASE_PTR (TPM0)
6249 /** Peripheral TPM1 base address */
6250 #define TPM1_BASE (0x40039000u)
6251 /** Peripheral TPM1 base pointer */
6252 #define TPM1 ((TPM_Type *)TPM1_BASE)
6253 #define TPM1_BASE_PTR (TPM1)
6254 /** Peripheral TPM2 base address */
6255 #define TPM2_BASE (0x4003A000u)
6256 /** Peripheral TPM2 base pointer */
6257 #define TPM2 ((TPM_Type *)TPM2_BASE)
6258 #define TPM2_BASE_PTR (TPM2)
6259 /** Array initializer of TPM peripheral base addresses */
6260 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
6261 /** Array initializer of TPM peripheral base pointers */
6262 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
6263 /** Interrupt vectors for the TPM peripheral type */
6264 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
6265 
6266 /* ----------------------------------------------------------------------------
6267  -- TPM - Register accessor macros
6268  ---------------------------------------------------------------------------- */
6269 
6270 /*!
6271  * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
6272  * @{
6273  */
6274 
6275 
6276 /* TPM - Register instance definitions */
6277 /* TPM0 */
6278 #define TPM0_SC TPM_SC_REG(TPM0)
6279 #define TPM0_CNT TPM_CNT_REG(TPM0)
6280 #define TPM0_MOD TPM_MOD_REG(TPM0)
6281 #define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
6282 #define TPM0_C0V TPM_CnV_REG(TPM0,0)
6283 #define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
6284 #define TPM0_C1V TPM_CnV_REG(TPM0,1)
6285 #define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
6286 #define TPM0_C2V TPM_CnV_REG(TPM0,2)
6287 #define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
6288 #define TPM0_C3V TPM_CnV_REG(TPM0,3)
6289 #define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
6290 #define TPM0_C4V TPM_CnV_REG(TPM0,4)
6291 #define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
6292 #define TPM0_C5V TPM_CnV_REG(TPM0,5)
6293 #define TPM0_STATUS TPM_STATUS_REG(TPM0)
6294 #define TPM0_CONF TPM_CONF_REG(TPM0)
6295 /* TPM1 */
6296 #define TPM1_SC TPM_SC_REG(TPM1)
6297 #define TPM1_CNT TPM_CNT_REG(TPM1)
6298 #define TPM1_MOD TPM_MOD_REG(TPM1)
6299 #define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
6300 #define TPM1_C0V TPM_CnV_REG(TPM1,0)
6301 #define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
6302 #define TPM1_C1V TPM_CnV_REG(TPM1,1)
6303 #define TPM1_STATUS TPM_STATUS_REG(TPM1)
6304 #define TPM1_CONF TPM_CONF_REG(TPM1)
6305 /* TPM2 */
6306 #define TPM2_SC TPM_SC_REG(TPM2)
6307 #define TPM2_CNT TPM_CNT_REG(TPM2)
6308 #define TPM2_MOD TPM_MOD_REG(TPM2)
6309 #define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
6310 #define TPM2_C0V TPM_CnV_REG(TPM2,0)
6311 #define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
6312 #define TPM2_C1V TPM_CnV_REG(TPM2,1)
6313 #define TPM2_STATUS TPM_STATUS_REG(TPM2)
6314 #define TPM2_CONF TPM_CONF_REG(TPM2)
6315 
6316 /* TPM - Register array accessors */
6317 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
6318 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
6319 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
6320 #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
6321 #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
6322 #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
6323 
6324 /*!
6325  * @}
6326  */ /* end of group TPM_Register_Accessor_Macros */
6327 
6328 
6329 /*!
6330  * @}
6331  */ /* end of group TPM_Peripheral_Access_Layer */
6332 
6333 
6334 /* ----------------------------------------------------------------------------
6335  -- TSI Peripheral Access Layer
6336  ---------------------------------------------------------------------------- */
6337 
6338 /*!
6339  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
6340  * @{
6341  */
6342 
6343 /** TSI - Register Layout Typedef */
6344 typedef struct {
6345  __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
6346  __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
6347  __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
6348 } TSI_Type, *TSI_MemMapPtr;
6349 
6350 /* ----------------------------------------------------------------------------
6351  -- TSI - Register accessor macros
6352  ---------------------------------------------------------------------------- */
6353 
6354 /*!
6355  * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
6356  * @{
6357  */
6358 
6359 
6360 /* TSI - Register accessors */
6361 #define TSI_GENCS_REG(base) ((base)->GENCS)
6362 #define TSI_DATA_REG(base) ((base)->DATA)
6363 #define TSI_TSHD_REG(base) ((base)->TSHD)
6364 
6365 /*!
6366  * @}
6367  */ /* end of group TSI_Register_Accessor_Macros */
6368 
6369 
6370 /* ----------------------------------------------------------------------------
6371  -- TSI Register Masks
6372  ---------------------------------------------------------------------------- */
6373 
6374 /*!
6375  * @addtogroup TSI_Register_Masks TSI Register Masks
6376  * @{
6377  */
6378 
6379 /* GENCS Bit Fields */
6380 #define TSI_GENCS_CURSW_MASK 0x2u
6381 #define TSI_GENCS_CURSW_SHIFT 1
6382 #define TSI_GENCS_CURSW_WIDTH 1
6383 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_CURSW_SHIFT))&TSI_GENCS_CURSW_MASK)
6384 #define TSI_GENCS_EOSF_MASK 0x4u
6385 #define TSI_GENCS_EOSF_SHIFT 2
6386 #define TSI_GENCS_EOSF_WIDTH 1
6387 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EOSF_SHIFT))&TSI_GENCS_EOSF_MASK)
6388 #define TSI_GENCS_SCNIP_MASK 0x8u
6389 #define TSI_GENCS_SCNIP_SHIFT 3
6390 #define TSI_GENCS_SCNIP_WIDTH 1
6391 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_SCNIP_SHIFT))&TSI_GENCS_SCNIP_MASK)
6392 #define TSI_GENCS_STM_MASK 0x10u
6393 #define TSI_GENCS_STM_SHIFT 4
6394 #define TSI_GENCS_STM_WIDTH 1
6395 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_STM_SHIFT))&TSI_GENCS_STM_MASK)
6396 #define TSI_GENCS_STPE_MASK 0x20u
6397 #define TSI_GENCS_STPE_SHIFT 5
6398 #define TSI_GENCS_STPE_WIDTH 1
6399 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_STPE_SHIFT))&TSI_GENCS_STPE_MASK)
6400 #define TSI_GENCS_TSIIEN_MASK 0x40u
6401 #define TSI_GENCS_TSIIEN_SHIFT 6
6402 #define TSI_GENCS_TSIIEN_WIDTH 1
6403 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_TSIIEN_SHIFT))&TSI_GENCS_TSIIEN_MASK)
6404 #define TSI_GENCS_TSIEN_MASK 0x80u
6405 #define TSI_GENCS_TSIEN_SHIFT 7
6406 #define TSI_GENCS_TSIEN_WIDTH 1
6407 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_TSIEN_SHIFT))&TSI_GENCS_TSIEN_MASK)
6408 #define TSI_GENCS_NSCN_MASK 0x1F00u
6409 #define TSI_GENCS_NSCN_SHIFT 8
6410 #define TSI_GENCS_NSCN_WIDTH 5
6411 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
6412 #define TSI_GENCS_PS_MASK 0xE000u
6413 #define TSI_GENCS_PS_SHIFT 13
6414 #define TSI_GENCS_PS_WIDTH 3
6415 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
6416 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
6417 #define TSI_GENCS_EXTCHRG_SHIFT 16
6418 #define TSI_GENCS_EXTCHRG_WIDTH 3
6419 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
6420 #define TSI_GENCS_DVOLT_MASK 0x180000u
6421 #define TSI_GENCS_DVOLT_SHIFT 19
6422 #define TSI_GENCS_DVOLT_WIDTH 2
6423 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
6424 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
6425 #define TSI_GENCS_REFCHRG_SHIFT 21
6426 #define TSI_GENCS_REFCHRG_WIDTH 3
6427 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
6428 #define TSI_GENCS_MODE_MASK 0xF000000u
6429 #define TSI_GENCS_MODE_SHIFT 24
6430 #define TSI_GENCS_MODE_WIDTH 4
6431 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
6432 #define TSI_GENCS_ESOR_MASK 0x10000000u
6433 #define TSI_GENCS_ESOR_SHIFT 28
6434 #define TSI_GENCS_ESOR_WIDTH 1
6435 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_ESOR_SHIFT))&TSI_GENCS_ESOR_MASK)
6436 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
6437 #define TSI_GENCS_OUTRGF_SHIFT 31
6438 #define TSI_GENCS_OUTRGF_WIDTH 1
6439 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_OUTRGF_SHIFT))&TSI_GENCS_OUTRGF_MASK)
6440 /* DATA Bit Fields */
6441 #define TSI_DATA_TSICNT_MASK 0xFFFFu
6442 #define TSI_DATA_TSICNT_SHIFT 0
6443 #define TSI_DATA_TSICNT_WIDTH 16
6444 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
6445 #define TSI_DATA_SWTS_MASK 0x400000u
6446 #define TSI_DATA_SWTS_SHIFT 22
6447 #define TSI_DATA_SWTS_WIDTH 1
6448 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_SWTS_SHIFT))&TSI_DATA_SWTS_MASK)
6449 #define TSI_DATA_DMAEN_MASK 0x800000u
6450 #define TSI_DATA_DMAEN_SHIFT 23
6451 #define TSI_DATA_DMAEN_WIDTH 1
6452 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_DMAEN_SHIFT))&TSI_DATA_DMAEN_MASK)
6453 #define TSI_DATA_TSICH_MASK 0xF0000000u
6454 #define TSI_DATA_TSICH_SHIFT 28
6455 #define TSI_DATA_TSICH_WIDTH 4
6456 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
6457 /* TSHD Bit Fields */
6458 #define TSI_TSHD_THRESL_MASK 0xFFFFu
6459 #define TSI_TSHD_THRESL_SHIFT 0
6460 #define TSI_TSHD_THRESL_WIDTH 16
6461 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
6462 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
6463 #define TSI_TSHD_THRESH_SHIFT 16
6464 #define TSI_TSHD_THRESH_WIDTH 16
6465 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
6466 
6467 /*!
6468  * @}
6469  */ /* end of group TSI_Register_Masks */
6470 
6471 
6472 /* TSI - Peripheral instance base addresses */
6473 /** Peripheral TSI0 base address */
6474 #define TSI0_BASE (0x40045000u)
6475 /** Peripheral TSI0 base pointer */
6476 #define TSI0 ((TSI_Type *)TSI0_BASE)
6477 #define TSI0_BASE_PTR (TSI0)
6478 /** Array initializer of TSI peripheral base addresses */
6479 #define TSI_BASE_ADDRS { TSI0_BASE }
6480 /** Array initializer of TSI peripheral base pointers */
6481 #define TSI_BASE_PTRS { TSI0 }
6482 /** Interrupt vectors for the TSI peripheral type */
6483 #define TSI_IRQS { TSI0_IRQn }
6484 
6485 /* ----------------------------------------------------------------------------
6486  -- TSI - Register accessor macros
6487  ---------------------------------------------------------------------------- */
6488 
6489 /*!
6490  * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
6491  * @{
6492  */
6493 
6494 
6495 /* TSI - Register instance definitions */
6496 /* TSI0 */
6497 #define TSI0_GENCS TSI_GENCS_REG(TSI0)
6498 #define TSI0_DATA TSI_DATA_REG(TSI0)
6499 #define TSI0_TSHD TSI_TSHD_REG(TSI0)
6500 
6501 /*!
6502  * @}
6503  */ /* end of group TSI_Register_Accessor_Macros */
6504 
6505 
6506 /*!
6507  * @}
6508  */ /* end of group TSI_Peripheral_Access_Layer */
6509 
6510 
6511 /* ----------------------------------------------------------------------------
6512  -- UART Peripheral Access Layer
6513  ---------------------------------------------------------------------------- */
6514 
6515 /*!
6516  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
6517  * @{
6518  */
6519 
6520 /** UART - Register Layout Typedef */
6521 typedef struct {
6522  __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
6523  __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
6524  __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
6525  __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
6526  __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
6527  __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
6528  __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
6529  __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
6530  __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
6531 } UART_Type, *UART_MemMapPtr;
6532 
6533 /* ----------------------------------------------------------------------------
6534  -- UART - Register accessor macros
6535  ---------------------------------------------------------------------------- */
6536 
6537 /*!
6538  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
6539  * @{
6540  */
6541 
6542 
6543 /* UART - Register accessors */
6544 #define UART_BDH_REG(base) ((base)->BDH)
6545 #define UART_BDL_REG(base) ((base)->BDL)
6546 #define UART_C1_REG(base) ((base)->C1)
6547 #define UART_C2_REG(base) ((base)->C2)
6548 #define UART_S1_REG(base) ((base)->S1)
6549 #define UART_S2_REG(base) ((base)->S2)
6550 #define UART_C3_REG(base) ((base)->C3)
6551 #define UART_D_REG(base) ((base)->D)
6552 #define UART_C4_REG(base) ((base)->C4)
6553 
6554 /*!
6555  * @}
6556  */ /* end of group UART_Register_Accessor_Macros */
6557 
6558 
6559 /* ----------------------------------------------------------------------------
6560  -- UART Register Masks
6561  ---------------------------------------------------------------------------- */
6562 
6563 /*!
6564  * @addtogroup UART_Register_Masks UART Register Masks
6565  * @{
6566  */
6567 
6568 /* BDH Bit Fields */
6569 #define UART_BDH_SBR_MASK 0x1Fu
6570 #define UART_BDH_SBR_SHIFT 0
6571 #define UART_BDH_SBR_WIDTH 5
6572 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
6573 #define UART_BDH_SBNS_MASK 0x20u
6574 #define UART_BDH_SBNS_SHIFT 5
6575 #define UART_BDH_SBNS_WIDTH 1
6576 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
6577 #define UART_BDH_RXEDGIE_MASK 0x40u
6578 #define UART_BDH_RXEDGIE_SHIFT 6
6579 #define UART_BDH_RXEDGIE_WIDTH 1
6580 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
6581 #define UART_BDH_LBKDIE_MASK 0x80u
6582 #define UART_BDH_LBKDIE_SHIFT 7
6583 #define UART_BDH_LBKDIE_WIDTH 1
6584 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
6585 /* BDL Bit Fields */
6586 #define UART_BDL_SBR_MASK 0xFFu
6587 #define UART_BDL_SBR_SHIFT 0
6588 #define UART_BDL_SBR_WIDTH 8
6589 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
6590 /* C1 Bit Fields */
6591 #define UART_C1_PT_MASK 0x1u
6592 #define UART_C1_PT_SHIFT 0
6593 #define UART_C1_PT_WIDTH 1
6594 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
6595 #define UART_C1_PE_MASK 0x2u
6596 #define UART_C1_PE_SHIFT 1
6597 #define UART_C1_PE_WIDTH 1
6598 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
6599 #define UART_C1_ILT_MASK 0x4u
6600 #define UART_C1_ILT_SHIFT 2
6601 #define UART_C1_ILT_WIDTH 1
6602 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
6603 #define UART_C1_WAKE_MASK 0x8u
6604 #define UART_C1_WAKE_SHIFT 3
6605 #define UART_C1_WAKE_WIDTH 1
6606 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
6607 #define UART_C1_M_MASK 0x10u
6608 #define UART_C1_M_SHIFT 4
6609 #define UART_C1_M_WIDTH 1
6610 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
6611 #define UART_C1_RSRC_MASK 0x20u
6612 #define UART_C1_RSRC_SHIFT 5
6613 #define UART_C1_RSRC_WIDTH 1
6614 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
6615 #define UART_C1_UARTSWAI_MASK 0x40u
6616 #define UART_C1_UARTSWAI_SHIFT 6
6617 #define UART_C1_UARTSWAI_WIDTH 1
6618 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
6619 #define UART_C1_LOOPS_MASK 0x80u
6620 #define UART_C1_LOOPS_SHIFT 7
6621 #define UART_C1_LOOPS_WIDTH 1
6622 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
6623 /* C2 Bit Fields */
6624 #define UART_C2_SBK_MASK 0x1u
6625 #define UART_C2_SBK_SHIFT 0
6626 #define UART_C2_SBK_WIDTH 1
6627 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
6628 #define UART_C2_RWU_MASK 0x2u
6629 #define UART_C2_RWU_SHIFT 1
6630 #define UART_C2_RWU_WIDTH 1
6631 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
6632 #define UART_C2_RE_MASK 0x4u
6633 #define UART_C2_RE_SHIFT 2
6634 #define UART_C2_RE_WIDTH 1
6635 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
6636 #define UART_C2_TE_MASK 0x8u
6637 #define UART_C2_TE_SHIFT 3
6638 #define UART_C2_TE_WIDTH 1
6639 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
6640 #define UART_C2_ILIE_MASK 0x10u
6641 #define UART_C2_ILIE_SHIFT 4
6642 #define UART_C2_ILIE_WIDTH 1
6643 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
6644 #define UART_C2_RIE_MASK 0x20u
6645 #define UART_C2_RIE_SHIFT 5
6646 #define UART_C2_RIE_WIDTH 1
6647 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
6648 #define UART_C2_TCIE_MASK 0x40u
6649 #define UART_C2_TCIE_SHIFT 6
6650 #define UART_C2_TCIE_WIDTH 1
6651 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
6652 #define UART_C2_TIE_MASK 0x80u
6653 #define UART_C2_TIE_SHIFT 7
6654 #define UART_C2_TIE_WIDTH 1
6655 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
6656 /* S1 Bit Fields */
6657 #define UART_S1_PF_MASK 0x1u
6658 #define UART_S1_PF_SHIFT 0
6659 #define UART_S1_PF_WIDTH 1
6660 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
6661 #define UART_S1_FE_MASK 0x2u
6662 #define UART_S1_FE_SHIFT 1
6663 #define UART_S1_FE_WIDTH 1
6664 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
6665 #define UART_S1_NF_MASK 0x4u
6666 #define UART_S1_NF_SHIFT 2
6667 #define UART_S1_NF_WIDTH 1
6668 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
6669 #define UART_S1_OR_MASK 0x8u
6670 #define UART_S1_OR_SHIFT 3
6671 #define UART_S1_OR_WIDTH 1
6672 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
6673 #define UART_S1_IDLE_MASK 0x10u
6674 #define UART_S1_IDLE_SHIFT 4
6675 #define UART_S1_IDLE_WIDTH 1
6676 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
6677 #define UART_S1_RDRF_MASK 0x20u
6678 #define UART_S1_RDRF_SHIFT 5
6679 #define UART_S1_RDRF_WIDTH 1
6680 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
6681 #define UART_S1_TC_MASK 0x40u
6682 #define UART_S1_TC_SHIFT 6
6683 #define UART_S1_TC_WIDTH 1
6684 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
6685 #define UART_S1_TDRE_MASK 0x80u
6686 #define UART_S1_TDRE_SHIFT 7
6687 #define UART_S1_TDRE_WIDTH 1
6688 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
6689 /* S2 Bit Fields */
6690 #define UART_S2_RAF_MASK 0x1u
6691 #define UART_S2_RAF_SHIFT 0
6692 #define UART_S2_RAF_WIDTH 1
6693 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
6694 #define UART_S2_LBKDE_MASK 0x2u
6695 #define UART_S2_LBKDE_SHIFT 1
6696 #define UART_S2_LBKDE_WIDTH 1
6697 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
6698 #define UART_S2_BRK13_MASK 0x4u
6699 #define UART_S2_BRK13_SHIFT 2
6700 #define UART_S2_BRK13_WIDTH 1
6701 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
6702 #define UART_S2_RWUID_MASK 0x8u
6703 #define UART_S2_RWUID_SHIFT 3
6704 #define UART_S2_RWUID_WIDTH 1
6705 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
6706 #define UART_S2_RXINV_MASK 0x10u
6707 #define UART_S2_RXINV_SHIFT 4
6708 #define UART_S2_RXINV_WIDTH 1
6709 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
6710 #define UART_S2_RXEDGIF_MASK 0x40u
6711 #define UART_S2_RXEDGIF_SHIFT 6
6712 #define UART_S2_RXEDGIF_WIDTH 1
6713 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
6714 #define UART_S2_LBKDIF_MASK 0x80u
6715 #define UART_S2_LBKDIF_SHIFT 7
6716 #define UART_S2_LBKDIF_WIDTH 1
6717 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
6718 /* C3 Bit Fields */
6719 #define UART_C3_PEIE_MASK 0x1u
6720 #define UART_C3_PEIE_SHIFT 0
6721 #define UART_C3_PEIE_WIDTH 1
6722 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
6723 #define UART_C3_FEIE_MASK 0x2u
6724 #define UART_C3_FEIE_SHIFT 1
6725 #define UART_C3_FEIE_WIDTH 1
6726 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
6727 #define UART_C3_NEIE_MASK 0x4u
6728 #define UART_C3_NEIE_SHIFT 2
6729 #define UART_C3_NEIE_WIDTH 1
6730 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
6731 #define UART_C3_ORIE_MASK 0x8u
6732 #define UART_C3_ORIE_SHIFT 3
6733 #define UART_C3_ORIE_WIDTH 1
6734 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
6735 #define UART_C3_TXINV_MASK 0x10u
6736 #define UART_C3_TXINV_SHIFT 4
6737 #define UART_C3_TXINV_WIDTH 1
6738 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
6739 #define UART_C3_TXDIR_MASK 0x20u
6740 #define UART_C3_TXDIR_SHIFT 5
6741 #define UART_C3_TXDIR_WIDTH 1
6742 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
6743 #define UART_C3_T8_MASK 0x40u
6744 #define UART_C3_T8_SHIFT 6
6745 #define UART_C3_T8_WIDTH 1
6746 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
6747 #define UART_C3_R8_MASK 0x80u
6748 #define UART_C3_R8_SHIFT 7
6749 #define UART_C3_R8_WIDTH 1
6750 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
6751 /* D Bit Fields */
6752 #define UART_D_R0T0_MASK 0x1u
6753 #define UART_D_R0T0_SHIFT 0
6754 #define UART_D_R0T0_WIDTH 1
6755 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R0T0_SHIFT))&UART_D_R0T0_MASK)
6756 #define UART_D_R1T1_MASK 0x2u
6757 #define UART_D_R1T1_SHIFT 1
6758 #define UART_D_R1T1_WIDTH 1
6759 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R1T1_SHIFT))&UART_D_R1T1_MASK)
6760 #define UART_D_R2T2_MASK 0x4u
6761 #define UART_D_R2T2_SHIFT 2
6762 #define UART_D_R2T2_WIDTH 1
6763 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R2T2_SHIFT))&UART_D_R2T2_MASK)
6764 #define UART_D_R3T3_MASK 0x8u
6765 #define UART_D_R3T3_SHIFT 3
6766 #define UART_D_R3T3_WIDTH 1
6767 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R3T3_SHIFT))&UART_D_R3T3_MASK)
6768 #define UART_D_R4T4_MASK 0x10u
6769 #define UART_D_R4T4_SHIFT 4
6770 #define UART_D_R4T4_WIDTH 1
6771 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R4T4_SHIFT))&UART_D_R4T4_MASK)
6772 #define UART_D_R5T5_MASK 0x20u
6773 #define UART_D_R5T5_SHIFT 5
6774 #define UART_D_R5T5_WIDTH 1
6775 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R5T5_SHIFT))&UART_D_R5T5_MASK)
6776 #define UART_D_R6T6_MASK 0x40u
6777 #define UART_D_R6T6_SHIFT 6
6778 #define UART_D_R6T6_WIDTH 1
6779 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R6T6_SHIFT))&UART_D_R6T6_MASK)
6780 #define UART_D_R7T7_MASK 0x80u
6781 #define UART_D_R7T7_SHIFT 7
6782 #define UART_D_R7T7_WIDTH 1
6783 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x))<<UART_D_R7T7_SHIFT))&UART_D_R7T7_MASK)
6784 /* C4 Bit Fields */
6785 #define UART_C4_RDMAS_MASK 0x20u
6786 #define UART_C4_RDMAS_SHIFT 5
6787 #define UART_C4_RDMAS_WIDTH 1
6788 #define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_RDMAS_SHIFT))&UART_C4_RDMAS_MASK)
6789 #define UART_C4_TDMAS_MASK 0x80u
6790 #define UART_C4_TDMAS_SHIFT 7
6791 #define UART_C4_TDMAS_WIDTH 1
6792 #define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_TDMAS_SHIFT))&UART_C4_TDMAS_MASK)
6793 
6794 /*!
6795  * @}
6796  */ /* end of group UART_Register_Masks */
6797 
6798 
6799 /* UART - Peripheral instance base addresses */
6800 /** Peripheral UART1 base address */
6801 #define UART1_BASE (0x4006B000u)
6802 /** Peripheral UART1 base pointer */
6803 #define UART1 ((UART_Type *)UART1_BASE)
6804 #define UART1_BASE_PTR (UART1)
6805 /** Peripheral UART2 base address */
6806 #define UART2_BASE (0x4006C000u)
6807 /** Peripheral UART2 base pointer */
6808 #define UART2 ((UART_Type *)UART2_BASE)
6809 #define UART2_BASE_PTR (UART2)
6810 /** Array initializer of UART peripheral base addresses */
6811 #define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE }
6812 /** Array initializer of UART peripheral base pointers */
6813 #define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 }
6814 /** Interrupt vectors for the UART peripheral type */
6815 #define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
6816 #define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
6817 
6818 /* ----------------------------------------------------------------------------
6819  -- UART - Register accessor macros
6820  ---------------------------------------------------------------------------- */
6821 
6822 /*!
6823  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
6824  * @{
6825  */
6826 
6827 
6828 /* UART - Register instance definitions */
6829 /* UART1 */
6830 #define UART1_BDH UART_BDH_REG(UART1)
6831 #define UART1_BDL UART_BDL_REG(UART1)
6832 #define UART1_C1 UART_C1_REG(UART1)
6833 #define UART1_C2 UART_C2_REG(UART1)
6834 #define UART1_S1 UART_S1_REG(UART1)
6835 #define UART1_S2 UART_S2_REG(UART1)
6836 #define UART1_C3 UART_C3_REG(UART1)
6837 #define UART1_D UART_D_REG(UART1)
6838 #define UART1_C4 UART_C4_REG(UART1)
6839 /* UART2 */
6840 #define UART2_BDH UART_BDH_REG(UART2)
6841 #define UART2_BDL UART_BDL_REG(UART2)
6842 #define UART2_C1 UART_C1_REG(UART2)
6843 #define UART2_C2 UART_C2_REG(UART2)
6844 #define UART2_S1 UART_S1_REG(UART2)
6845 #define UART2_S2 UART_S2_REG(UART2)
6846 #define UART2_C3 UART_C3_REG(UART2)
6847 #define UART2_D UART_D_REG(UART2)
6848 #define UART2_C4 UART_C4_REG(UART2)
6849 
6850 /*!
6851  * @}
6852  */ /* end of group UART_Register_Accessor_Macros */
6853 
6854 
6855 /*!
6856  * @}
6857  */ /* end of group UART_Peripheral_Access_Layer */
6858 
6859 
6860 /* ----------------------------------------------------------------------------
6861  -- UART0 Peripheral Access Layer
6862  ---------------------------------------------------------------------------- */
6863 
6864 /*!
6865  * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
6866  * @{
6867  */
6868 
6869 /** UART0 - Register Layout Typedef */
6870 typedef struct {
6871  __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
6872  __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
6873  __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
6874  __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
6875  __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
6876  __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
6877  __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
6878  __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
6879  __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
6880  __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
6881  __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
6882  __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
6883 } UART0_Type, *UART0_MemMapPtr;
6884 
6885 /* ----------------------------------------------------------------------------
6886  -- UART0 - Register accessor macros
6887  ---------------------------------------------------------------------------- */
6888 
6889 /*!
6890  * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros
6891  * @{
6892  */
6893 
6894 
6895 /* UART0 - Register accessors */
6896 #define UART0_BDH_REG(base) ((base)->BDH)
6897 #define UART0_BDL_REG(base) ((base)->BDL)
6898 #define UART0_C1_REG(base) ((base)->C1)
6899 #define UART0_C2_REG(base) ((base)->C2)
6900 #define UART0_S1_REG(base) ((base)->S1)
6901 #define UART0_S2_REG(base) ((base)->S2)
6902 #define UART0_C3_REG(base) ((base)->C3)
6903 #define UART0_D_REG(base) ((base)->D)
6904 #define UART0_MA1_REG(base) ((base)->MA1)
6905 #define UART0_MA2_REG(base) ((base)->MA2)
6906 #define UART0_C4_REG(base) ((base)->C4)
6907 #define UART0_C5_REG(base) ((base)->C5)
6908 
6909 /*!
6910  * @}
6911  */ /* end of group UART0_Register_Accessor_Macros */
6912 
6913 
6914 /* ----------------------------------------------------------------------------
6915  -- UART0 Register Masks
6916  ---------------------------------------------------------------------------- */
6917 
6918 /*!
6919  * @addtogroup UART0_Register_Masks UART0 Register Masks
6920  * @{
6921  */
6922 
6923 /* BDH Bit Fields */
6924 #define UART0_BDH_SBR_MASK 0x1Fu
6925 #define UART0_BDH_SBR_SHIFT 0
6926 #define UART0_BDH_SBR_WIDTH 5
6927 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
6928 #define UART0_BDH_SBNS_MASK 0x20u
6929 #define UART0_BDH_SBNS_SHIFT 5
6930 #define UART0_BDH_SBNS_WIDTH 1
6931 #define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBNS_SHIFT))&UART0_BDH_SBNS_MASK)
6932 #define UART0_BDH_RXEDGIE_MASK 0x40u
6933 #define UART0_BDH_RXEDGIE_SHIFT 6
6934 #define UART0_BDH_RXEDGIE_WIDTH 1
6935 #define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_RXEDGIE_SHIFT))&UART0_BDH_RXEDGIE_MASK)
6936 #define UART0_BDH_LBKDIE_MASK 0x80u
6937 #define UART0_BDH_LBKDIE_SHIFT 7
6938 #define UART0_BDH_LBKDIE_WIDTH 1
6939 #define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_LBKDIE_SHIFT))&UART0_BDH_LBKDIE_MASK)
6940 /* BDL Bit Fields */
6941 #define UART0_BDL_SBR_MASK 0xFFu
6942 #define UART0_BDL_SBR_SHIFT 0
6943 #define UART0_BDL_SBR_WIDTH 8
6944 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
6945 /* C1 Bit Fields */
6946 #define UART0_C1_PT_MASK 0x1u
6947 #define UART0_C1_PT_SHIFT 0
6948 #define UART0_C1_PT_WIDTH 1
6949 #define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_PT_SHIFT))&UART0_C1_PT_MASK)
6950 #define UART0_C1_PE_MASK 0x2u
6951 #define UART0_C1_PE_SHIFT 1
6952 #define UART0_C1_PE_WIDTH 1
6953 #define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_PE_SHIFT))&UART0_C1_PE_MASK)
6954 #define UART0_C1_ILT_MASK 0x4u
6955 #define UART0_C1_ILT_SHIFT 2
6956 #define UART0_C1_ILT_WIDTH 1
6957 #define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_ILT_SHIFT))&UART0_C1_ILT_MASK)
6958 #define UART0_C1_WAKE_MASK 0x8u
6959 #define UART0_C1_WAKE_SHIFT 3
6960 #define UART0_C1_WAKE_WIDTH 1
6961 #define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_WAKE_SHIFT))&UART0_C1_WAKE_MASK)
6962 #define UART0_C1_M_MASK 0x10u
6963 #define UART0_C1_M_SHIFT 4
6964 #define UART0_C1_M_WIDTH 1
6965 #define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_M_SHIFT))&UART0_C1_M_MASK)
6966 #define UART0_C1_RSRC_MASK 0x20u
6967 #define UART0_C1_RSRC_SHIFT 5
6968 #define UART0_C1_RSRC_WIDTH 1
6969 #define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_RSRC_SHIFT))&UART0_C1_RSRC_MASK)
6970 #define UART0_C1_DOZEEN_MASK 0x40u
6971 #define UART0_C1_DOZEEN_SHIFT 6
6972 #define UART0_C1_DOZEEN_WIDTH 1
6973 #define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_DOZEEN_SHIFT))&UART0_C1_DOZEEN_MASK)
6974 #define UART0_C1_LOOPS_MASK 0x80u
6975 #define UART0_C1_LOOPS_SHIFT 7
6976 #define UART0_C1_LOOPS_WIDTH 1
6977 #define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART0_C1_LOOPS_SHIFT))&UART0_C1_LOOPS_MASK)
6978 /* C2 Bit Fields */
6979 #define UART0_C2_SBK_MASK 0x1u
6980 #define UART0_C2_SBK_SHIFT 0
6981 #define UART0_C2_SBK_WIDTH 1
6982 #define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_SBK_SHIFT))&UART0_C2_SBK_MASK)
6983 #define UART0_C2_RWU_MASK 0x2u
6984 #define UART0_C2_RWU_SHIFT 1
6985 #define UART0_C2_RWU_WIDTH 1
6986 #define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_RWU_SHIFT))&UART0_C2_RWU_MASK)
6987 #define UART0_C2_RE_MASK 0x4u
6988 #define UART0_C2_RE_SHIFT 2
6989 #define UART0_C2_RE_WIDTH 1
6990 #define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_RE_SHIFT))&UART0_C2_RE_MASK)
6991 #define UART0_C2_TE_MASK 0x8u
6992 #define UART0_C2_TE_SHIFT 3
6993 #define UART0_C2_TE_WIDTH 1
6994 #define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_TE_SHIFT))&UART0_C2_TE_MASK)
6995 #define UART0_C2_ILIE_MASK 0x10u
6996 #define UART0_C2_ILIE_SHIFT 4
6997 #define UART0_C2_ILIE_WIDTH 1
6998 #define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_ILIE_SHIFT))&UART0_C2_ILIE_MASK)
6999 #define UART0_C2_RIE_MASK 0x20u
7000 #define UART0_C2_RIE_SHIFT 5
7001 #define UART0_C2_RIE_WIDTH 1
7002 #define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_RIE_SHIFT))&UART0_C2_RIE_MASK)
7003 #define UART0_C2_TCIE_MASK 0x40u
7004 #define UART0_C2_TCIE_SHIFT 6
7005 #define UART0_C2_TCIE_WIDTH 1
7006 #define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_TCIE_SHIFT))&UART0_C2_TCIE_MASK)
7007 #define UART0_C2_TIE_MASK 0x80u
7008 #define UART0_C2_TIE_SHIFT 7
7009 #define UART0_C2_TIE_WIDTH 1
7010 #define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C2_TIE_SHIFT))&UART0_C2_TIE_MASK)
7011 /* S1 Bit Fields */
7012 #define UART0_S1_PF_MASK 0x1u
7013 #define UART0_S1_PF_SHIFT 0
7014 #define UART0_S1_PF_WIDTH 1
7015 #define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_PF_SHIFT))&UART0_S1_PF_MASK)
7016 #define UART0_S1_FE_MASK 0x2u
7017 #define UART0_S1_FE_SHIFT 1
7018 #define UART0_S1_FE_WIDTH 1
7019 #define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_FE_SHIFT))&UART0_S1_FE_MASK)
7020 #define UART0_S1_NF_MASK 0x4u
7021 #define UART0_S1_NF_SHIFT 2
7022 #define UART0_S1_NF_WIDTH 1
7023 #define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_NF_SHIFT))&UART0_S1_NF_MASK)
7024 #define UART0_S1_OR_MASK 0x8u
7025 #define UART0_S1_OR_SHIFT 3
7026 #define UART0_S1_OR_WIDTH 1
7027 #define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_OR_SHIFT))&UART0_S1_OR_MASK)
7028 #define UART0_S1_IDLE_MASK 0x10u
7029 #define UART0_S1_IDLE_SHIFT 4
7030 #define UART0_S1_IDLE_WIDTH 1
7031 #define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_IDLE_SHIFT))&UART0_S1_IDLE_MASK)
7032 #define UART0_S1_RDRF_MASK 0x20u
7033 #define UART0_S1_RDRF_SHIFT 5
7034 #define UART0_S1_RDRF_WIDTH 1
7035 #define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_RDRF_SHIFT))&UART0_S1_RDRF_MASK)
7036 #define UART0_S1_TC_MASK 0x40u
7037 #define UART0_S1_TC_SHIFT 6
7038 #define UART0_S1_TC_WIDTH 1
7039 #define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_TC_SHIFT))&UART0_S1_TC_MASK)
7040 #define UART0_S1_TDRE_MASK 0x80u
7041 #define UART0_S1_TDRE_SHIFT 7
7042 #define UART0_S1_TDRE_WIDTH 1
7043 #define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART0_S1_TDRE_SHIFT))&UART0_S1_TDRE_MASK)
7044 /* S2 Bit Fields */
7045 #define UART0_S2_RAF_MASK 0x1u
7046 #define UART0_S2_RAF_SHIFT 0
7047 #define UART0_S2_RAF_WIDTH 1
7048 #define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_RAF_SHIFT))&UART0_S2_RAF_MASK)
7049 #define UART0_S2_LBKDE_MASK 0x2u
7050 #define UART0_S2_LBKDE_SHIFT 1
7051 #define UART0_S2_LBKDE_WIDTH 1
7052 #define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_LBKDE_SHIFT))&UART0_S2_LBKDE_MASK)
7053 #define UART0_S2_BRK13_MASK 0x4u
7054 #define UART0_S2_BRK13_SHIFT 2
7055 #define UART0_S2_BRK13_WIDTH 1
7056 #define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_BRK13_SHIFT))&UART0_S2_BRK13_MASK)
7057 #define UART0_S2_RWUID_MASK 0x8u
7058 #define UART0_S2_RWUID_SHIFT 3
7059 #define UART0_S2_RWUID_WIDTH 1
7060 #define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_RWUID_SHIFT))&UART0_S2_RWUID_MASK)
7061 #define UART0_S2_RXINV_MASK 0x10u
7062 #define UART0_S2_RXINV_SHIFT 4
7063 #define UART0_S2_RXINV_WIDTH 1
7064 #define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_RXINV_SHIFT))&UART0_S2_RXINV_MASK)
7065 #define UART0_S2_MSBF_MASK 0x20u
7066 #define UART0_S2_MSBF_SHIFT 5
7067 #define UART0_S2_MSBF_WIDTH 1
7068 #define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_MSBF_SHIFT))&UART0_S2_MSBF_MASK)
7069 #define UART0_S2_RXEDGIF_MASK 0x40u
7070 #define UART0_S2_RXEDGIF_SHIFT 6
7071 #define UART0_S2_RXEDGIF_WIDTH 1
7072 #define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_RXEDGIF_SHIFT))&UART0_S2_RXEDGIF_MASK)
7073 #define UART0_S2_LBKDIF_MASK 0x80u
7074 #define UART0_S2_LBKDIF_SHIFT 7
7075 #define UART0_S2_LBKDIF_WIDTH 1
7076 #define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART0_S2_LBKDIF_SHIFT))&UART0_S2_LBKDIF_MASK)
7077 /* C3 Bit Fields */
7078 #define UART0_C3_PEIE_MASK 0x1u
7079 #define UART0_C3_PEIE_SHIFT 0
7080 #define UART0_C3_PEIE_WIDTH 1
7081 #define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_PEIE_SHIFT))&UART0_C3_PEIE_MASK)
7082 #define UART0_C3_FEIE_MASK 0x2u
7083 #define UART0_C3_FEIE_SHIFT 1
7084 #define UART0_C3_FEIE_WIDTH 1
7085 #define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_FEIE_SHIFT))&UART0_C3_FEIE_MASK)
7086 #define UART0_C3_NEIE_MASK 0x4u
7087 #define UART0_C3_NEIE_SHIFT 2
7088 #define UART0_C3_NEIE_WIDTH 1
7089 #define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_NEIE_SHIFT))&UART0_C3_NEIE_MASK)
7090 #define UART0_C3_ORIE_MASK 0x8u
7091 #define UART0_C3_ORIE_SHIFT 3
7092 #define UART0_C3_ORIE_WIDTH 1
7093 #define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_ORIE_SHIFT))&UART0_C3_ORIE_MASK)
7094 #define UART0_C3_TXINV_MASK 0x10u
7095 #define UART0_C3_TXINV_SHIFT 4
7096 #define UART0_C3_TXINV_WIDTH 1
7097 #define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_TXINV_SHIFT))&UART0_C3_TXINV_MASK)
7098 #define UART0_C3_TXDIR_MASK 0x20u
7099 #define UART0_C3_TXDIR_SHIFT 5
7100 #define UART0_C3_TXDIR_WIDTH 1
7101 #define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_TXDIR_SHIFT))&UART0_C3_TXDIR_MASK)
7102 #define UART0_C3_R9T8_MASK 0x40u
7103 #define UART0_C3_R9T8_SHIFT 6
7104 #define UART0_C3_R9T8_WIDTH 1
7105 #define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_R9T8_SHIFT))&UART0_C3_R9T8_MASK)
7106 #define UART0_C3_R8T9_MASK 0x80u
7107 #define UART0_C3_R8T9_SHIFT 7
7108 #define UART0_C3_R8T9_WIDTH 1
7109 #define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x))<<UART0_C3_R8T9_SHIFT))&UART0_C3_R8T9_MASK)
7110 /* D Bit Fields */
7111 #define UART0_D_R0T0_MASK 0x1u
7112 #define UART0_D_R0T0_SHIFT 0
7113 #define UART0_D_R0T0_WIDTH 1
7114 #define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R0T0_SHIFT))&UART0_D_R0T0_MASK)
7115 #define UART0_D_R1T1_MASK 0x2u
7116 #define UART0_D_R1T1_SHIFT 1
7117 #define UART0_D_R1T1_WIDTH 1
7118 #define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R1T1_SHIFT))&UART0_D_R1T1_MASK)
7119 #define UART0_D_R2T2_MASK 0x4u
7120 #define UART0_D_R2T2_SHIFT 2
7121 #define UART0_D_R2T2_WIDTH 1
7122 #define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R2T2_SHIFT))&UART0_D_R2T2_MASK)
7123 #define UART0_D_R3T3_MASK 0x8u
7124 #define UART0_D_R3T3_SHIFT 3
7125 #define UART0_D_R3T3_WIDTH 1
7126 #define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R3T3_SHIFT))&UART0_D_R3T3_MASK)
7127 #define UART0_D_R4T4_MASK 0x10u
7128 #define UART0_D_R4T4_SHIFT 4
7129 #define UART0_D_R4T4_WIDTH 1
7130 #define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R4T4_SHIFT))&UART0_D_R4T4_MASK)
7131 #define UART0_D_R5T5_MASK 0x20u
7132 #define UART0_D_R5T5_SHIFT 5
7133 #define UART0_D_R5T5_WIDTH 1
7134 #define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R5T5_SHIFT))&UART0_D_R5T5_MASK)
7135 #define UART0_D_R6T6_MASK 0x40u
7136 #define UART0_D_R6T6_SHIFT 6
7137 #define UART0_D_R6T6_WIDTH 1
7138 #define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R6T6_SHIFT))&UART0_D_R6T6_MASK)
7139 #define UART0_D_R7T7_MASK 0x80u
7140 #define UART0_D_R7T7_SHIFT 7
7141 #define UART0_D_R7T7_WIDTH 1
7142 #define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x))<<UART0_D_R7T7_SHIFT))&UART0_D_R7T7_MASK)
7143 /* MA1 Bit Fields */
7144 #define UART0_MA1_MA_MASK 0xFFu
7145 #define UART0_MA1_MA_SHIFT 0
7146 #define UART0_MA1_MA_WIDTH 8
7147 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
7148 /* MA2 Bit Fields */
7149 #define UART0_MA2_MA_MASK 0xFFu
7150 #define UART0_MA2_MA_SHIFT 0
7151 #define UART0_MA2_MA_WIDTH 8
7152 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
7153 /* C4 Bit Fields */
7154 #define UART0_C4_OSR_MASK 0x1Fu
7155 #define UART0_C4_OSR_SHIFT 0
7156 #define UART0_C4_OSR_WIDTH 5
7157 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
7158 #define UART0_C4_M10_MASK 0x20u
7159 #define UART0_C4_M10_SHIFT 5
7160 #define UART0_C4_M10_WIDTH 1
7161 #define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_M10_SHIFT))&UART0_C4_M10_MASK)
7162 #define UART0_C4_MAEN2_MASK 0x40u
7163 #define UART0_C4_MAEN2_SHIFT 6
7164 #define UART0_C4_MAEN2_WIDTH 1
7165 #define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_MAEN2_SHIFT))&UART0_C4_MAEN2_MASK)
7166 #define UART0_C4_MAEN1_MASK 0x80u
7167 #define UART0_C4_MAEN1_SHIFT 7
7168 #define UART0_C4_MAEN1_WIDTH 1
7169 #define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_MAEN1_SHIFT))&UART0_C4_MAEN1_MASK)
7170 /* C5 Bit Fields */
7171 #define UART0_C5_RESYNCDIS_MASK 0x1u
7172 #define UART0_C5_RESYNCDIS_SHIFT 0
7173 #define UART0_C5_RESYNCDIS_WIDTH 1
7174 #define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x))<<UART0_C5_RESYNCDIS_SHIFT))&UART0_C5_RESYNCDIS_MASK)
7175 #define UART0_C5_BOTHEDGE_MASK 0x2u
7176 #define UART0_C5_BOTHEDGE_SHIFT 1
7177 #define UART0_C5_BOTHEDGE_WIDTH 1
7178 #define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C5_BOTHEDGE_SHIFT))&UART0_C5_BOTHEDGE_MASK)
7179 #define UART0_C5_RDMAE_MASK 0x20u
7180 #define UART0_C5_RDMAE_SHIFT 5
7181 #define UART0_C5_RDMAE_WIDTH 1
7182 #define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C5_RDMAE_SHIFT))&UART0_C5_RDMAE_MASK)
7183 #define UART0_C5_TDMAE_MASK 0x80u
7184 #define UART0_C5_TDMAE_SHIFT 7
7185 #define UART0_C5_TDMAE_WIDTH 1
7186 #define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x))<<UART0_C5_TDMAE_SHIFT))&UART0_C5_TDMAE_MASK)
7187 
7188 /*!
7189  * @}
7190  */ /* end of group UART0_Register_Masks */
7191 
7192 
7193 /* UART0 - Peripheral instance base addresses */
7194 /** Peripheral UART0 base address */
7195 #define UART0_BASE (0x4006A000u)
7196 /** Peripheral UART0 base pointer */
7197 #define UART0 ((UART0_Type *)UART0_BASE)
7198 #define UART0_BASE_PTR (UART0)
7199 /** Array initializer of UART0 peripheral base addresses */
7200 #define UART0_BASE_ADDRS { UART0_BASE }
7201 /** Array initializer of UART0 peripheral base pointers */
7202 #define UART0_BASE_PTRS { UART0 }
7203 /** Interrupt vectors for the UART0 peripheral type */
7204 #define UART0_RX_TX_IRQS { UART0_IRQn }
7205 #define UART0_ERR_IRQS { UART0_IRQn }
7206 
7207 /* ----------------------------------------------------------------------------
7208  -- UART0 - Register accessor macros
7209  ---------------------------------------------------------------------------- */
7210 
7211 /*!
7212  * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros
7213  * @{
7214  */
7215 
7216 
7217 /* UART0 - Register instance definitions */
7218 /* UART0 */
7219 #define UART0_BDH UART0_BDH_REG(UART0)
7220 #define UART0_BDL UART0_BDL_REG(UART0)
7221 #define UART0_C1 UART0_C1_REG(UART0)
7222 #define UART0_C2 UART0_C2_REG(UART0)
7223 #define UART0_S1 UART0_S1_REG(UART0)
7224 #define UART0_S2 UART0_S2_REG(UART0)
7225 #define UART0_C3 UART0_C3_REG(UART0)
7226 #define UART0_D UART0_D_REG(UART0)
7227 #define UART0_MA1 UART0_MA1_REG(UART0)
7228 #define UART0_MA2 UART0_MA2_REG(UART0)
7229 #define UART0_C4 UART0_C4_REG(UART0)
7230 #define UART0_C5 UART0_C5_REG(UART0)
7231 
7232 /*!
7233  * @}
7234  */ /* end of group UART0_Register_Accessor_Macros */
7235 
7236 
7237 /*!
7238  * @}
7239  */ /* end of group UART0_Peripheral_Access_Layer */
7240 
7241 
7242 /* ----------------------------------------------------------------------------
7243  -- USB Peripheral Access Layer
7244  ---------------------------------------------------------------------------- */
7245 
7246 /*!
7247  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
7248  * @{
7249  */
7250 
7251 /** USB - Register Layout Typedef */
7252 typedef struct {
7253  __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
7254  uint8_t RESERVED_0[3];
7255  __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
7256  uint8_t RESERVED_1[3];
7257  __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
7258  uint8_t RESERVED_2[3];
7259  __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
7260  uint8_t RESERVED_3[3];
7261  __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
7262  uint8_t RESERVED_4[3];
7263  __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
7264  uint8_t RESERVED_5[3];
7265  __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
7266  uint8_t RESERVED_6[3];
7267  __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
7268  uint8_t RESERVED_7[99];
7269  __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
7270  uint8_t RESERVED_8[3];
7271  __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
7272  uint8_t RESERVED_9[3];
7273  __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
7274  uint8_t RESERVED_10[3];
7275  __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
7276  uint8_t RESERVED_11[3];
7277  __I uint8_t STAT; /**< Status register, offset: 0x90 */
7278  uint8_t RESERVED_12[3];
7279  __IO uint8_t CTL; /**< Control register, offset: 0x94 */
7280  uint8_t RESERVED_13[3];
7281  __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
7282  uint8_t RESERVED_14[3];
7283  __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
7284  uint8_t RESERVED_15[3];
7285  __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
7286  uint8_t RESERVED_16[3];
7287  __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
7288  uint8_t RESERVED_17[3];
7289  __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
7290  uint8_t RESERVED_18[3];
7291  __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
7292  uint8_t RESERVED_19[3];
7293  __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
7294  uint8_t RESERVED_20[3];
7295  __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
7296  uint8_t RESERVED_21[11];
7297  struct { /* offset: 0xC0, array step: 0x4 */
7298  __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
7299  uint8_t RESERVED_0[3];
7300  } ENDPOINT[16];
7301  __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
7302  uint8_t RESERVED_22[3];
7303  __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
7304  uint8_t RESERVED_23[3];
7305  __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
7306  uint8_t RESERVED_24[3];
7307  __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
7308  uint8_t RESERVED_25[7];
7309  __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
7310 } USB_Type, *USB_MemMapPtr;
7311 
7312 /* ----------------------------------------------------------------------------
7313  -- USB - Register accessor macros
7314  ---------------------------------------------------------------------------- */
7315 
7316 /*!
7317  * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
7318  * @{
7319  */
7320 
7321 
7322 /* USB - Register accessors */
7323 #define USB_PERID_REG(base) ((base)->PERID)
7324 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
7325 #define USB_REV_REG(base) ((base)->REV)
7326 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
7327 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
7328 #define USB_OTGICR_REG(base) ((base)->OTGICR)
7329 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
7330 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
7331 #define USB_ISTAT_REG(base) ((base)->ISTAT)
7332 #define USB_INTEN_REG(base) ((base)->INTEN)
7333 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
7334 #define USB_ERREN_REG(base) ((base)->ERREN)
7335 #define USB_STAT_REG(base) ((base)->STAT)
7336 #define USB_CTL_REG(base) ((base)->CTL)
7337 #define USB_ADDR_REG(base) ((base)->ADDR)
7338 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
7339 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
7340 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
7341 #define USB_TOKEN_REG(base) ((base)->TOKEN)
7342 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
7343 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
7344 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
7345 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
7346 #define USB_ENDPT_COUNT 16
7347 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
7348 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
7349 #define USB_CONTROL_REG(base) ((base)->CONTROL)
7350 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
7351 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
7352 
7353 /*!
7354  * @}
7355  */ /* end of group USB_Register_Accessor_Macros */
7356 
7357 
7358 /* ----------------------------------------------------------------------------
7359  -- USB Register Masks
7360  ---------------------------------------------------------------------------- */
7361 
7362 /*!
7363  * @addtogroup USB_Register_Masks USB Register Masks
7364  * @{
7365  */
7366 
7367 /* PERID Bit Fields */
7368 #define USB_PERID_ID_MASK 0x3Fu
7369 #define USB_PERID_ID_SHIFT 0
7370 #define USB_PERID_ID_WIDTH 6
7371 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
7372 /* IDCOMP Bit Fields */
7373 #define USB_IDCOMP_NID_MASK 0x3Fu
7374 #define USB_IDCOMP_NID_SHIFT 0
7375 #define USB_IDCOMP_NID_WIDTH 6
7376 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
7377 /* REV Bit Fields */
7378 #define USB_REV_REV_MASK 0xFFu
7379 #define USB_REV_REV_SHIFT 0
7380 #define USB_REV_REV_WIDTH 8
7381 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
7382 /* ADDINFO Bit Fields */
7383 #define USB_ADDINFO_IEHOST_MASK 0x1u
7384 #define USB_ADDINFO_IEHOST_SHIFT 0
7385 #define USB_ADDINFO_IEHOST_WIDTH 1
7386 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
7387 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
7388 #define USB_ADDINFO_IRQNUM_SHIFT 3
7389 #define USB_ADDINFO_IRQNUM_WIDTH 5
7390 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
7391 /* OTGISTAT Bit Fields */
7392 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
7393 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
7394 #define USB_OTGISTAT_AVBUSCHG_WIDTH 1
7395 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
7396 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
7397 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
7398 #define USB_OTGISTAT_B_SESS_CHG_WIDTH 1
7399 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
7400 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
7401 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
7402 #define USB_OTGISTAT_SESSVLDCHG_WIDTH 1
7403 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
7404 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
7405 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
7406 #define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
7407 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
7408 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
7409 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
7410 #define USB_OTGISTAT_ONEMSEC_WIDTH 1
7411 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
7412 #define USB_OTGISTAT_IDCHG_MASK 0x80u
7413 #define USB_OTGISTAT_IDCHG_SHIFT 7
7414 #define USB_OTGISTAT_IDCHG_WIDTH 1
7415 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
7416 /* OTGICR Bit Fields */
7417 #define USB_OTGICR_AVBUSEN_MASK 0x1u
7418 #define USB_OTGICR_AVBUSEN_SHIFT 0
7419 #define USB_OTGICR_AVBUSEN_WIDTH 1
7420 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
7421 #define USB_OTGICR_BSESSEN_MASK 0x4u
7422 #define USB_OTGICR_BSESSEN_SHIFT 2
7423 #define USB_OTGICR_BSESSEN_WIDTH 1
7424 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
7425 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
7426 #define USB_OTGICR_SESSVLDEN_SHIFT 3
7427 #define USB_OTGICR_SESSVLDEN_WIDTH 1
7428 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
7429 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
7430 #define USB_OTGICR_LINESTATEEN_SHIFT 5
7431 #define USB_OTGICR_LINESTATEEN_WIDTH 1
7432 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
7433 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
7434 #define USB_OTGICR_ONEMSECEN_SHIFT 6
7435 #define USB_OTGICR_ONEMSECEN_WIDTH 1
7436 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
7437 #define USB_OTGICR_IDEN_MASK 0x80u
7438 #define USB_OTGICR_IDEN_SHIFT 7
7439 #define USB_OTGICR_IDEN_WIDTH 1
7440 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
7441 /* OTGSTAT Bit Fields */
7442 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
7443 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
7444 #define USB_OTGSTAT_AVBUSVLD_WIDTH 1
7445 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
7446 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
7447 #define USB_OTGSTAT_BSESSEND_SHIFT 2
7448 #define USB_OTGSTAT_BSESSEND_WIDTH 1
7449 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
7450 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
7451 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
7452 #define USB_OTGSTAT_SESS_VLD_WIDTH 1
7453 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
7454 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
7455 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
7456 #define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
7457 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
7458 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
7459 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
7460 #define USB_OTGSTAT_ONEMSECEN_WIDTH 1
7461 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
7462 #define USB_OTGSTAT_ID_MASK 0x80u
7463 #define USB_OTGSTAT_ID_SHIFT 7
7464 #define USB_OTGSTAT_ID_WIDTH 1
7465 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
7466 /* OTGCTL Bit Fields */
7467 #define USB_OTGCTL_OTGEN_MASK 0x4u
7468 #define USB_OTGCTL_OTGEN_SHIFT 2
7469 #define USB_OTGCTL_OTGEN_WIDTH 1
7470 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
7471 #define USB_OTGCTL_DMLOW_MASK 0x10u
7472 #define USB_OTGCTL_DMLOW_SHIFT 4
7473 #define USB_OTGCTL_DMLOW_WIDTH 1
7474 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
7475 #define USB_OTGCTL_DPLOW_MASK 0x20u
7476 #define USB_OTGCTL_DPLOW_SHIFT 5
7477 #define USB_OTGCTL_DPLOW_WIDTH 1
7478 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
7479 #define USB_OTGCTL_DPHIGH_MASK 0x80u
7480 #define USB_OTGCTL_DPHIGH_SHIFT 7
7481 #define USB_OTGCTL_DPHIGH_WIDTH 1
7482 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
7483 /* ISTAT Bit Fields */
7484 #define USB_ISTAT_USBRST_MASK 0x1u
7485 #define USB_ISTAT_USBRST_SHIFT 0
7486 #define USB_ISTAT_USBRST_WIDTH 1
7487 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
7488 #define USB_ISTAT_ERROR_MASK 0x2u
7489 #define USB_ISTAT_ERROR_SHIFT 1
7490 #define USB_ISTAT_ERROR_WIDTH 1
7491 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
7492 #define USB_ISTAT_SOFTOK_MASK 0x4u
7493 #define USB_ISTAT_SOFTOK_SHIFT 2
7494 #define USB_ISTAT_SOFTOK_WIDTH 1
7495 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
7496 #define USB_ISTAT_TOKDNE_MASK 0x8u
7497 #define USB_ISTAT_TOKDNE_SHIFT 3
7498 #define USB_ISTAT_TOKDNE_WIDTH 1
7499 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
7500 #define USB_ISTAT_SLEEP_MASK 0x10u
7501 #define USB_ISTAT_SLEEP_SHIFT 4
7502 #define USB_ISTAT_SLEEP_WIDTH 1
7503 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
7504 #define USB_ISTAT_RESUME_MASK 0x20u
7505 #define USB_ISTAT_RESUME_SHIFT 5
7506 #define USB_ISTAT_RESUME_WIDTH 1
7507 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
7508 #define USB_ISTAT_ATTACH_MASK 0x40u
7509 #define USB_ISTAT_ATTACH_SHIFT 6
7510 #define USB_ISTAT_ATTACH_WIDTH 1
7511 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
7512 #define USB_ISTAT_STALL_MASK 0x80u
7513 #define USB_ISTAT_STALL_SHIFT 7
7514 #define USB_ISTAT_STALL_WIDTH 1
7515 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
7516 /* INTEN Bit Fields */
7517 #define USB_INTEN_USBRSTEN_MASK 0x1u
7518 #define USB_INTEN_USBRSTEN_SHIFT 0
7519 #define USB_INTEN_USBRSTEN_WIDTH 1
7520 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
7521 #define USB_INTEN_ERROREN_MASK 0x2u
7522 #define USB_INTEN_ERROREN_SHIFT 1
7523 #define USB_INTEN_ERROREN_WIDTH 1
7524 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
7525 #define USB_INTEN_SOFTOKEN_MASK 0x4u
7526 #define USB_INTEN_SOFTOKEN_SHIFT 2
7527 #define USB_INTEN_SOFTOKEN_WIDTH 1
7528 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
7529 #define USB_INTEN_TOKDNEEN_MASK 0x8u
7530 #define USB_INTEN_TOKDNEEN_SHIFT 3
7531 #define USB_INTEN_TOKDNEEN_WIDTH 1
7532 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
7533 #define USB_INTEN_SLEEPEN_MASK 0x10u
7534 #define USB_INTEN_SLEEPEN_SHIFT 4
7535 #define USB_INTEN_SLEEPEN_WIDTH 1
7536 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
7537 #define USB_INTEN_RESUMEEN_MASK 0x20u
7538 #define USB_INTEN_RESUMEEN_SHIFT 5
7539 #define USB_INTEN_RESUMEEN_WIDTH 1
7540 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
7541 #define USB_INTEN_ATTACHEN_MASK 0x40u
7542 #define USB_INTEN_ATTACHEN_SHIFT 6
7543 #define USB_INTEN_ATTACHEN_WIDTH 1
7544 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
7545 #define USB_INTEN_STALLEN_MASK 0x80u
7546 #define USB_INTEN_STALLEN_SHIFT 7
7547 #define USB_INTEN_STALLEN_WIDTH 1
7548 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
7549 /* ERRSTAT Bit Fields */
7550 #define USB_ERRSTAT_PIDERR_MASK 0x1u
7551 #define USB_ERRSTAT_PIDERR_SHIFT 0
7552 #define USB_ERRSTAT_PIDERR_WIDTH 1
7553 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
7554 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
7555 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
7556 #define USB_ERRSTAT_CRC5EOF_WIDTH 1
7557 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
7558 #define USB_ERRSTAT_CRC16_MASK 0x4u
7559 #define USB_ERRSTAT_CRC16_SHIFT 2
7560 #define USB_ERRSTAT_CRC16_WIDTH 1
7561 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
7562 #define USB_ERRSTAT_DFN8_MASK 0x8u
7563 #define USB_ERRSTAT_DFN8_SHIFT 3
7564 #define USB_ERRSTAT_DFN8_WIDTH 1
7565 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
7566 #define USB_ERRSTAT_BTOERR_MASK 0x10u
7567 #define USB_ERRSTAT_BTOERR_SHIFT 4
7568 #define USB_ERRSTAT_BTOERR_WIDTH 1
7569 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
7570 #define USB_ERRSTAT_DMAERR_MASK 0x20u
7571 #define USB_ERRSTAT_DMAERR_SHIFT 5
7572 #define USB_ERRSTAT_DMAERR_WIDTH 1
7573 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
7574 #define USB_ERRSTAT_BTSERR_MASK 0x80u
7575 #define USB_ERRSTAT_BTSERR_SHIFT 7
7576 #define USB_ERRSTAT_BTSERR_WIDTH 1
7577 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
7578 /* ERREN Bit Fields */
7579 #define USB_ERREN_PIDERREN_MASK 0x1u
7580 #define USB_ERREN_PIDERREN_SHIFT 0
7581 #define USB_ERREN_PIDERREN_WIDTH 1
7582 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
7583 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
7584 #define USB_ERREN_CRC5EOFEN_SHIFT 1
7585 #define USB_ERREN_CRC5EOFEN_WIDTH 1
7586 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
7587 #define USB_ERREN_CRC16EN_MASK 0x4u
7588 #define USB_ERREN_CRC16EN_SHIFT 2
7589 #define USB_ERREN_CRC16EN_WIDTH 1
7590 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
7591 #define USB_ERREN_DFN8EN_MASK 0x8u
7592 #define USB_ERREN_DFN8EN_SHIFT 3
7593 #define USB_ERREN_DFN8EN_WIDTH 1
7594 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
7595 #define USB_ERREN_BTOERREN_MASK 0x10u
7596 #define USB_ERREN_BTOERREN_SHIFT 4
7597 #define USB_ERREN_BTOERREN_WIDTH 1
7598 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
7599 #define USB_ERREN_DMAERREN_MASK 0x20u
7600 #define USB_ERREN_DMAERREN_SHIFT 5
7601 #define USB_ERREN_DMAERREN_WIDTH 1
7602 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
7603 #define USB_ERREN_BTSERREN_MASK 0x80u
7604 #define USB_ERREN_BTSERREN_SHIFT 7
7605 #define USB_ERREN_BTSERREN_WIDTH 1
7606 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
7607 /* STAT Bit Fields */
7608 #define USB_STAT_ODD_MASK 0x4u
7609 #define USB_STAT_ODD_SHIFT 2
7610 #define USB_STAT_ODD_WIDTH 1
7611 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
7612 #define USB_STAT_TX_MASK 0x8u
7613 #define USB_STAT_TX_SHIFT 3
7614 #define USB_STAT_TX_WIDTH 1
7615 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
7616 #define USB_STAT_ENDP_MASK 0xF0u
7617 #define USB_STAT_ENDP_SHIFT 4
7618 #define USB_STAT_ENDP_WIDTH 4
7619 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
7620 /* CTL Bit Fields */
7621 #define USB_CTL_USBENSOFEN_MASK 0x1u
7622 #define USB_CTL_USBENSOFEN_SHIFT 0
7623 #define USB_CTL_USBENSOFEN_WIDTH 1
7624 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
7625 #define USB_CTL_ODDRST_MASK 0x2u
7626 #define USB_CTL_ODDRST_SHIFT 1
7627 #define USB_CTL_ODDRST_WIDTH 1
7628 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
7629 #define USB_CTL_RESUME_MASK 0x4u
7630 #define USB_CTL_RESUME_SHIFT 2
7631 #define USB_CTL_RESUME_WIDTH 1
7632 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
7633 #define USB_CTL_HOSTMODEEN_MASK 0x8u
7634 #define USB_CTL_HOSTMODEEN_SHIFT 3
7635 #define USB_CTL_HOSTMODEEN_WIDTH 1
7636 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
7637 #define USB_CTL_RESET_MASK 0x10u
7638 #define USB_CTL_RESET_SHIFT 4
7639 #define USB_CTL_RESET_WIDTH 1
7640 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
7641 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
7642 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
7643 #define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
7644 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
7645 #define USB_CTL_SE0_MASK 0x40u
7646 #define USB_CTL_SE0_SHIFT 6
7647 #define USB_CTL_SE0_WIDTH 1
7648 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
7649 #define USB_CTL_JSTATE_MASK 0x80u
7650 #define USB_CTL_JSTATE_SHIFT 7
7651 #define USB_CTL_JSTATE_WIDTH 1
7652 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
7653 /* ADDR Bit Fields */
7654 #define USB_ADDR_ADDR_MASK 0x7Fu
7655 #define USB_ADDR_ADDR_SHIFT 0
7656 #define USB_ADDR_ADDR_WIDTH 7
7657 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
7658 #define USB_ADDR_LSEN_MASK 0x80u
7659 #define USB_ADDR_LSEN_SHIFT 7
7660 #define USB_ADDR_LSEN_WIDTH 1
7661 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
7662 /* BDTPAGE1 Bit Fields */
7663 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
7664 #define USB_BDTPAGE1_BDTBA_SHIFT 1
7665 #define USB_BDTPAGE1_BDTBA_WIDTH 7
7666 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
7667 /* FRMNUML Bit Fields */
7668 #define USB_FRMNUML_FRM_MASK 0xFFu
7669 #define USB_FRMNUML_FRM_SHIFT 0
7670 #define USB_FRMNUML_FRM_WIDTH 8
7671 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
7672 /* FRMNUMH Bit Fields */
7673 #define USB_FRMNUMH_FRM_MASK 0x7u
7674 #define USB_FRMNUMH_FRM_SHIFT 0
7675 #define USB_FRMNUMH_FRM_WIDTH 3
7676 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
7677 /* TOKEN Bit Fields */
7678 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
7679 #define USB_TOKEN_TOKENENDPT_SHIFT 0
7680 #define USB_TOKEN_TOKENENDPT_WIDTH 4
7681 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
7682 #define USB_TOKEN_TOKENPID_MASK 0xF0u
7683 #define USB_TOKEN_TOKENPID_SHIFT 4
7684 #define USB_TOKEN_TOKENPID_WIDTH 4
7685 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
7686 /* SOFTHLD Bit Fields */
7687 #define USB_SOFTHLD_CNT_MASK 0xFFu
7688 #define USB_SOFTHLD_CNT_SHIFT 0
7689 #define USB_SOFTHLD_CNT_WIDTH 8
7690 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
7691 /* BDTPAGE2 Bit Fields */
7692 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
7693 #define USB_BDTPAGE2_BDTBA_SHIFT 0
7694 #define USB_BDTPAGE2_BDTBA_WIDTH 8
7695 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
7696 /* BDTPAGE3 Bit Fields */
7697 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
7698 #define USB_BDTPAGE3_BDTBA_SHIFT 0
7699 #define USB_BDTPAGE3_BDTBA_WIDTH 8
7700 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
7701 /* ENDPT Bit Fields */
7702 #define USB_ENDPT_EPHSHK_MASK 0x1u
7703 #define USB_ENDPT_EPHSHK_SHIFT 0
7704 #define USB_ENDPT_EPHSHK_WIDTH 1
7705 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
7706 #define USB_ENDPT_EPSTALL_MASK 0x2u
7707 #define USB_ENDPT_EPSTALL_SHIFT 1
7708 #define USB_ENDPT_EPSTALL_WIDTH 1
7709 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
7710 #define USB_ENDPT_EPTXEN_MASK 0x4u
7711 #define USB_ENDPT_EPTXEN_SHIFT 2
7712 #define USB_ENDPT_EPTXEN_WIDTH 1
7713 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
7714 #define USB_ENDPT_EPRXEN_MASK 0x8u
7715 #define USB_ENDPT_EPRXEN_SHIFT 3
7716 #define USB_ENDPT_EPRXEN_WIDTH 1
7717 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
7718 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
7719 #define USB_ENDPT_EPCTLDIS_SHIFT 4
7720 #define USB_ENDPT_EPCTLDIS_WIDTH 1
7721 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
7722 #define USB_ENDPT_RETRYDIS_MASK 0x40u
7723 #define USB_ENDPT_RETRYDIS_SHIFT 6
7724 #define USB_ENDPT_RETRYDIS_WIDTH 1
7725 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
7726 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
7727 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
7728 #define USB_ENDPT_HOSTWOHUB_WIDTH 1
7729 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
7730 /* USBCTRL Bit Fields */
7731 #define USB_USBCTRL_PDE_MASK 0x40u
7732 #define USB_USBCTRL_PDE_SHIFT 6
7733 #define USB_USBCTRL_PDE_WIDTH 1
7734 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
7735 #define USB_USBCTRL_SUSP_MASK 0x80u
7736 #define USB_USBCTRL_SUSP_SHIFT 7
7737 #define USB_USBCTRL_SUSP_WIDTH 1
7738 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
7739 /* OBSERVE Bit Fields */
7740 #define USB_OBSERVE_DMPD_MASK 0x10u
7741 #define USB_OBSERVE_DMPD_SHIFT 4
7742 #define USB_OBSERVE_DMPD_WIDTH 1
7743 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
7744 #define USB_OBSERVE_DPPD_MASK 0x40u
7745 #define USB_OBSERVE_DPPD_SHIFT 6
7746 #define USB_OBSERVE_DPPD_WIDTH 1
7747 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
7748 #define USB_OBSERVE_DPPU_MASK 0x80u
7749 #define USB_OBSERVE_DPPU_SHIFT 7
7750 #define USB_OBSERVE_DPPU_WIDTH 1
7751 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
7752 /* CONTROL Bit Fields */
7753 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
7754 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
7755 #define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
7756 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
7757 /* USBTRC0 Bit Fields */
7758 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
7759 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
7760 #define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
7761 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
7762 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
7763 #define USB_USBTRC0_SYNC_DET_SHIFT 1
7764 #define USB_USBTRC0_SYNC_DET_WIDTH 1
7765 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
7766 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
7767 #define USB_USBTRC0_USBRESMEN_SHIFT 5
7768 #define USB_USBTRC0_USBRESMEN_WIDTH 1
7769 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
7770 #define USB_USBTRC0_USBRESET_MASK 0x80u
7771 #define USB_USBTRC0_USBRESET_SHIFT 7
7772 #define USB_USBTRC0_USBRESET_WIDTH 1
7773 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
7774 /* USBFRMADJUST Bit Fields */
7775 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
7776 #define USB_USBFRMADJUST_ADJ_SHIFT 0
7777 #define USB_USBFRMADJUST_ADJ_WIDTH 8
7778 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
7779 
7780 /*!
7781  * @}
7782  */ /* end of group USB_Register_Masks */
7783 
7784 
7785 /* USB - Peripheral instance base addresses */
7786 /** Peripheral USB0 base address */
7787 #define USB0_BASE (0x40072000u)
7788 /** Peripheral USB0 base pointer */
7789 #define USB0 ((USB_Type *)USB0_BASE)
7790 #define USB0_BASE_PTR (USB0)
7791 /** Array initializer of USB peripheral base addresses */
7792 #define USB_BASE_ADDRS { USB0_BASE }
7793 /** Array initializer of USB peripheral base pointers */
7794 #define USB_BASE_PTRS { USB0 }
7795 /** Interrupt vectors for the USB peripheral type */
7796 #define USB_IRQS { USB0_IRQn }
7797 
7798 /* ----------------------------------------------------------------------------
7799  -- USB - Register accessor macros
7800  ---------------------------------------------------------------------------- */
7801 
7802 /*!
7803  * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
7804  * @{
7805  */
7806 
7807 
7808 /* USB - Register instance definitions */
7809 /* USB0 */
7810 #define USB0_PERID USB_PERID_REG(USB0)
7811 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
7812 #define USB0_REV USB_REV_REG(USB0)
7813 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
7814 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
7815 #define USB0_OTGICR USB_OTGICR_REG(USB0)
7816 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
7817 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
7818 #define USB0_ISTAT USB_ISTAT_REG(USB0)
7819 #define USB0_INTEN USB_INTEN_REG(USB0)
7820 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
7821 #define USB0_ERREN USB_ERREN_REG(USB0)
7822 #define USB0_STAT USB_STAT_REG(USB0)
7823 #define USB0_CTL USB_CTL_REG(USB0)
7824 #define USB0_ADDR USB_ADDR_REG(USB0)
7825 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
7826 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
7827 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
7828 #define USB0_TOKEN USB_TOKEN_REG(USB0)
7829 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
7830 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
7831 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
7832 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
7833 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
7834 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
7835 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
7836 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
7837 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
7838 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
7839 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
7840 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
7841 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
7842 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
7843 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
7844 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
7845 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
7846 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
7847 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
7848 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
7849 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
7850 #define USB0_CONTROL USB_CONTROL_REG(USB0)
7851 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
7852 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
7853 
7854 /* USB - Register array accessors */
7855 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
7856 
7857 /*!
7858  * @}
7859  */ /* end of group USB_Register_Accessor_Macros */
7860 
7861 
7862 /*!
7863  * @}
7864  */ /* end of group USB_Peripheral_Access_Layer */
7865 
7866 
7867 /*
7868 ** End of section using anonymous unions
7869 */
7870 
7871 #if defined(__ARMCC_VERSION)
7872  #pragma pop
7873 #elif defined(__CWCC__)
7874  #pragma pop
7875 #elif defined(__GNUC__)
7876  /* leave anonymous unions enabled */
7877 #elif defined(__IAR_SYSTEMS_ICC__)
7878  #pragma language=default
7879 #else
7880  #error Not supported compiler type
7881 #endif
7882 
7883 /*!
7884  * @}
7885  */ /* end of group Peripheral_access_layer */
7886 
7887 
7888 /* ----------------------------------------------------------------------------
7889  -- Backward Compatibility
7890  ---------------------------------------------------------------------------- */
7891 
7892 /*!
7893  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
7894  * @{
7895  */
7896 
7897 #define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
7898 #define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
7899 #define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
7900 #define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
7901 #define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
7902 #define DMA_REQC0 This_symbol_has_been_deprecated
7903 #define DMA_REQC1 This_symbol_has_been_deprecated
7904 #define DMA_REQC2 This_symbol_has_been_deprecated
7905 #define DMA_REQC3 This_symbol_has_been_deprecated
7906 #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
7907 #define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
7908 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
7909 #define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
7910 #define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
7911 #define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
7912 #define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
7913 #define UART_C4_LBKDDMAS_MASK This_symbol_has_been_deprecated
7914 #define UART_C4_LBKDDMAS_SHIFT This_symbol_has_been_deprecated
7915 #define UART_C4_ILDMAS_MASK This_symbol_has_been_deprecated
7916 #define UART_C4_ILDMAS_SHIFT This_symbol_has_been_deprecated
7917 #define UART_C4_TCDMAS_MASK This_symbol_has_been_deprecated
7918 #define UART_C4_TCDMAS_SHIFT This_symbol_has_been_deprecated
7919 #define UARTLP_Type UART0_Type
7920 #define UARTLP_BDH_REG UART0_BDH_REG
7921 #define UARTLP_BDL_REG UART0_BDL_REG
7922 #define UARTLP_C1_REG UART0_C1_REG
7923 #define UARTLP_C2_REG UART0_C2_REG
7924 #define UARTLP_S1_REG UART0_S1_REG
7925 #define UARTLP_S2_REG UART0_S2_REG
7926 #define UARTLP_C3_REG UART0_C3_REG
7927 #define UARTLP_D_REG UART0_D_REG
7928 #define UARTLP_MA1_REG UART0_MA1_REG
7929 #define UARTLP_MA2_REG UART0_MA2_REG
7930 #define UARTLP_C4_REG UART0_C4_REG
7931 #define UARTLP_C5_REG UART0_C5_REG
7932 #define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
7933 #define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
7934 #define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
7935 #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
7936 #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
7937 #define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
7938 #define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
7939 #define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
7940 #define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
7941 #define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
7942 #define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
7943 #define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
7944 #define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
7945 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
7946 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
7947 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
7948 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
7949 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
7950 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
7951 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
7952 #define UARTLP_C1_M_MASK UART0_C1_M_MASK
7953 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
7954 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
7955 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
7956 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
7957 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
7958 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
7959 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
7960 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
7961 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
7962 #define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
7963 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
7964 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
7965 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
7966 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
7967 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
7968 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
7969 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
7970 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
7971 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
7972 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
7973 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
7974 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
7975 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
7976 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
7977 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
7978 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
7979 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
7980 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
7981 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
7982 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
7983 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
7984 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
7985 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
7986 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
7987 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
7988 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
7989 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
7990 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
7991 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
7992 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
7993 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
7994 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
7995 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
7996 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
7997 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
7998 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
7999 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
8000 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
8001 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
8002 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
8003 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
8004 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
8005 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
8006 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
8007 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
8008 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
8009 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
8010 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
8011 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
8012 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
8013 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
8014 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
8015 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
8016 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
8017 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
8018 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
8019 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
8020 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
8021 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
8022 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
8023 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
8024 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
8025 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
8026 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
8027 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
8028 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
8029 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
8030 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
8031 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
8032 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
8033 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
8034 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
8035 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
8036 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
8037 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
8038 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
8039 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
8040 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
8041 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
8042 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
8043 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
8044 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
8045 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
8046 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
8047 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
8048 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
8049 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
8050 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
8051 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
8052 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
8053 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
8054 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
8055 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
8056 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
8057 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
8058 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
8059 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
8060 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
8061 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
8062 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
8063 #define UARTLP_BASES UARTLP_BASES
8064 #define NV_FOPT_EZPORT_DIS_MASK This_symbol_has_been_deprecated
8065 #define NV_FOPT_EZPORT_DIS_SHIFT This_symbol_has_been_deprecated
8066 #define ADC_BASES ADC_BASE_PTRS
8067 #define CMP_BASES CMP_BASE_PTRS
8068 #define DAC_BASES DAC_BASE_PTRS
8069 #define DMA_BASES DMA_BASE_PTRS
8070 #define DMAMUX_BASES DMAMUX_BASE_PTRS
8071 #define FPTA_BASE_PTR FGPIOA_BASE_PTR
8072 #define FPTA_BASE FGPIOA_BASE
8073 #define FPTA FGPIOA
8074 #define FPTB_BASE_PTR FGPIOB_BASE_PTR
8075 #define FPTB_BASE FGPIOB_BASE
8076 #define FPTB FGPIOB
8077 #define FPTC_BASE_PTR FGPIOC_BASE_PTR
8078 #define FPTC_BASE FGPIOC_BASE
8079 #define FPTC FGPIOC
8080 #define FPTD_BASE_PTR FGPIOD_BASE_PTR
8081 #define FPTD_BASE FGPIOD_BASE
8082 #define FPTD FGPIOD
8083 #define FPTE_BASE_PTR FGPIOE_BASE_PTR
8084 #define FPTE_BASE FGPIOE_BASE
8085 #define FPTE FGPIOE
8086 #define FGPIO_BASES FGPIO_BASE_PTRS
8087 #define FTFA_BASES FTFA_BASE_PTRS
8088 #define PTA_BASE_PTR GPIOA_BASE_PTR
8089 #define PTA_BASE GPIOA_BASE
8090 #define PTA GPIOA
8091 #define PTB_BASE_PTR GPIOB_BASE_PTR
8092 #define PTB_BASE GPIOB_BASE
8093 #define PTB GPIOB
8094 #define PTC_BASE_PTR GPIOC_BASE_PTR
8095 #define PTC_BASE GPIOC_BASE
8096 #define PTC GPIOC
8097 #define PTD_BASE_PTR GPIOD_BASE_PTR
8098 #define PTD_BASE GPIOD_BASE
8099 #define PTD GPIOD
8100 #define PTE_BASE_PTR GPIOE_BASE_PTR
8101 #define PTE_BASE GPIOE_BASE
8102 #define PTE GPIOE
8103 #define GPIO_BASES GPIO_BASE_PTRS
8104 #define I2C_BASES I2C_BASE_PTRS
8105 #define LLWU_BASES LLWU_BASE_PTRS
8106 #define LPTMR_BASES LPTMR_BASE_PTRS
8107 #define MCG_BASES MCG_BASE_PTRS
8108 #define MCM_BASES MCM_BASE_PTRS
8109 #define MTB_BASES MTB_BASE_PTRS
8110 #define MTBDWT_BASES MTBDWT_BASE_PTRS
8111 #define NV_BASES NV_BASES
8112 #define OSC_BASES OSC_BASE_PTRS
8113 #define PIT_BASES PIT_BASE_PTRS
8114 #define PMC_BASES PMC_BASE_PTRS
8115 #define PORT_BASES PORT_BASE_PTRS
8116 #define RCM_BASES RCM_BASE_PTRS
8117 #define ROM_BASES ROM_BASE_PTRS
8118 #define RTC_BASES RTC_BASE_PTRS
8119 #define SIM_BASES SIM_BASE_PTRS
8120 #define SMC_BASES SMC_BASE_PTRS
8121 #define SPI_BASES SPI_BASE_PTRS
8122 #define TPM_BASES TPM_BASE_PTRS
8123 #define TSI_BASES TSI_BASE_PTRS
8124 #define UART_BASES UART_BASE_PTRS
8125 #define UART0_BASES UART0_BASE_PTRS
8126 #define USB_BASES USB_BASE_PTRS
8127 #define LPTimer_IRQn LPTMR0_IRQn
8128 #define LPTimer_IRQHandler LPTMR0_IRQHandler
8129 #define LLW_IRQn LLWU_IRQn
8130 #define LLW_IRQHandler LLWU_IRQHandler
8131 
8132 /*!
8133  * @}
8134  */ /* end of group Backward_Compatibility_Symbols */
8135 
8136 
8137 #else /* #if !defined(MKL25Z4_H_) */
8138  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
8139  #if (MCU_MEM_MAP_VERSION != 0x0200u)
8140  #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
8141  #warning There are included two not compatible versions of memory maps. Please check possible differences.
8142  #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
8143  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
8144 #endif /* #if !defined(MKL25Z4_H_) */
8145 
8146 /* MKL25Z4.h, eof. */
8147 
USB_Type::ENDPT
__IO uint8_t ENDPT
Endpoint Control register, array offset: 0xC0, array step: 0x4.
Definition: MKL25Z4.h:7298
UART2_IRQn
UART2 status and error.
Definition: MKL25Z4.h:158
GPIO_Type::PSOR
__O uint32_t PSOR
Port Set Output Register, offset: 0x4.
Definition: MKL25Z4.h:1786
MCG_Type::C10
__I uint8_t C10
MCG Control 10 Register, offset: 0xF.
Definition: MKL25Z4.h:2772
IRQn
IRQn
Definition: MKL25Z4.h:132
GPIO_Type::PCOR
__O uint32_t PCOR
Port Clear Output Register, offset: 0x8.
Definition: MKL25Z4.h:1787
DMA_Type::SAR
__IO uint32_t SAR
Source Address Register, array offset: 0x100, array step: 0x10.
Definition: MKL25Z4.h:994
USB_Type::BDTPAGE1
__IO uint8_t BDTPAGE1
BDT Page Register 1, offset: 0x9C.
Definition: MKL25Z4.h:7283
LLWU_Type::PE1
__IO uint8_t PE1
LLWU Pin Enable 1 register, offset: 0x0.
Definition: MKL25Z4.h:2275
UART0_Type::S2
__IO uint8_t S2
UART Status Register 2, offset: 0x5.
Definition: MKL25Z4.h:6876
core_cm0plus.h
CMSIS Cortex-M0+ Core Peripheral Access Layer Header File.
TPM_Type::STATUS
__IO uint32_t STATUS
Capture and Compare Status, offset: 0x50.
Definition: MKL25Z4.h:6070
USB_Type::IDCOMP
__I uint8_t IDCOMP
Peripheral ID Complement register, offset: 0x4.
Definition: MKL25Z4.h:7255
RTC_Type::TCR
__IO uint32_t TCR
RTC Time Compensation Register, offset: 0xC.
Definition: MKL25Z4.h:5026
GPIO_Type::PDDR
__IO uint32_t PDDR
Port Data Direction Register, offset: 0x14.
Definition: MKL25Z4.h:1790
MCM_Type
MCM - Register Layout Typedef.
Definition: MKL25Z4.h:3066
SIM_Type::SOPT4
__IO uint32_t SOPT4
System Options Register 4, offset: 0x100C.
Definition: MKL25Z4.h:5262
MCM_Type::CPO
__IO uint32_t CPO
Compute Operation Control Register, offset: 0x40.
Definition: MKL25Z4.h:3072
MCM_Type::PLAMC
__I uint16_t PLAMC
Crossbar Switch (AXBS) Master Configuration, offset: 0xA.
Definition: MKL25Z4.h:3069
NV_Type::FPROT3
__I uint8_t FPROT3
Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8.
Definition: MKL25Z4.h:3701
FTFA_Type::FCCOBB
__IO uint8_t FCCOBB
Flash Common Command Object Registers, offset: 0xC.
Definition: MKL25Z4.h:1516
MCG_Type::C8
__IO uint8_t C8
MCG Control 8 Register, offset: 0xD.
Definition: MKL25Z4.h:2770
DAC_Type::DATL
__IO uint8_t DATL
DAC Data Low Register, array offset: 0x0, array step: 0x2.
Definition: MKL25Z4.h:813
SMC_Type::PMPROT
__IO uint8_t PMPROT
Power Mode Protection register, offset: 0x0.
Definition: MKL25Z4.h:5716
USB_Type::BDTPAGE3
__IO uint8_t BDTPAGE3
BDT Page Register 3, offset: 0xB4.
Definition: MKL25Z4.h:7295
TSI0_IRQn
TSI0 interrupt.
Definition: MKL25Z4.h:170
ADC_Type::CV2
__IO uint32_t CV2
Compare Value Registers, offset: 0x1C.
Definition: MKL25Z4.h:250
SIM_Type::CLKDIV1
__IO uint32_t CLKDIV1
System Clock Divider Register 1, offset: 0x1044.
Definition: MKL25Z4.h:5273
GPIO_Type::PDOR
__IO uint32_t PDOR
Port Data Output Register, offset: 0x0.
Definition: MKL25Z4.h:1785
NotAvail_IRQn
Not available device specific interrupt.
Definition: MKL25Z4.h:134
ADC_Type::CFG1
__IO uint32_t CFG1
ADC Configuration Register 1, offset: 0x8.
Definition: MKL25Z4.h:246
ADC_Type::CLP2
__IO uint32_t CLP2
ADC Plus-Side General Calibration Value Register, offset: 0x44.
Definition: MKL25Z4.h:260
MTBDWT_Type::FCT
__IO uint32_t FCT
MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28...
Definition: MKL25Z4.h:3488
ROM_Type::PERIPHID3
__I uint32_t PERIPHID3
Peripheral ID Register, offset: 0xFEC.
Definition: MKL25Z4.h:4847
DMAMUX_Type
DMAMUX - Register Layout Typedef.
Definition: MKL25Z4.h:1226
NonMaskableInt_IRQn
Non Maskable Interrupt.
Definition: MKL25Z4.h:137
CMP0_IRQn
CMP0 interrupt.
Definition: MKL25Z4.h:160
MTBDWT_Type
MTBDWT - Register Layout Typedef.
Definition: MKL25Z4.h:3482
MTB_Type::BASE
__I uint32_t BASE
MTB Base Register, offset: 0xC.
Definition: MKL25Z4.h:3219
MCG_Type::C9
__I uint8_t C9
MCG Control 9 Register, offset: 0xE.
Definition: MKL25Z4.h:2771
PIT_Type::MCR
__IO uint32_t MCR
PIT Module Control Register, offset: 0x0.
Definition: MKL25Z4.h:4019
SIM_Type::SOPT7
__IO uint32_t SOPT7
System Options Register 7, offset: 0x1018.
Definition: MKL25Z4.h:5265
GPIO_Type::PDIR
__I uint32_t PDIR
Port Data Input Register, offset: 0x10.
Definition: MKL25Z4.h:1789
RCM_Type
RCM - Register Layout Typedef.
Definition: MKL25Z4.h:4683
TPM_Type::CnSC
__IO uint32_t CnSC
Channel (n) Status and Control, array offset: 0xC, array step: 0x8.
Definition: MKL25Z4.h:6066
NV_Type::BACKKEY0
__I uint8_t BACKKEY0
Backdoor Comparison Key 0., offset: 0x3.
Definition: MKL25Z4.h:3696
FTFA_Type::FCCOB0
__IO uint8_t FCCOB0
Flash Common Command Object Registers, offset: 0x7.
Definition: MKL25Z4.h:1511
SIM_Type::UIDMH
__I uint32_t UIDMH
Unique Identification Register Mid-High, offset: 0x1058.
Definition: MKL25Z4.h:5278
TPM0_IRQn
TPM0 single interrupt vector for all sources.
Definition: MKL25Z4.h:161
USB_Type::FRMNUML
__IO uint8_t FRMNUML
Frame Number Register Low, offset: 0xA0.
Definition: MKL25Z4.h:7285
USB_Type::USBFRMADJUST
__IO uint8_t USBFRMADJUST
Frame Adjust Register, offset: 0x114.
Definition: MKL25Z4.h:7309
LLWU_Type::F3
__I uint8_t F3
LLWU Flag 3 register, offset: 0x7.
Definition: MKL25Z4.h:2282
NV_Type::BACKKEY2
__I uint8_t BACKKEY2
Backdoor Comparison Key 2., offset: 0x1.
Definition: MKL25Z4.h:3694
I2C_Type::SLTL
__IO uint8_t SLTL
I2C SCL Low Timeout Register Low, offset: 0xB.
Definition: MKL25Z4.h:1971
FTFA_IRQn
Command complete and read collision.
Definition: MKL25Z4.h:149
I2C_Type::F
__IO uint8_t F
I2C Frequency Divider register, offset: 0x1.
Definition: MKL25Z4.h:1961
DAC_Type
DAC - Register Layout Typedef.
Definition: MKL25Z4.h:811
PORT_Type::GPCLR
__O uint32_t GPCLR
Global Pin Control Low Register, offset: 0x80.
Definition: MKL25Z4.h:4332
SPI_Type::BR
__IO uint8_t BR
SPI baud rate register, offset: 0x2.
Definition: MKL25Z4.h:5853
UART_Type::S2
__IO uint8_t S2
UART Status Register 2, offset: 0x5.
Definition: MKL25Z4.h:6527
MTB_Type::MASTER
__IO uint32_t MASTER
MTB Master Register, offset: 0x4.
Definition: MKL25Z4.h:3217
USB_Type::PERID
__I uint8_t PERID
Peripheral ID register, offset: 0x0.
Definition: MKL25Z4.h:7253
PendSV_IRQn
Cortex-M0 Pend SV Interrupt.
Definition: MKL25Z4.h:140
UART_Type
UART - Register Layout Typedef.
Definition: MKL25Z4.h:6521
LVD_LVW_IRQn
Low-voltage detect, low-voltage warning.
Definition: MKL25Z4.h:150
SIM_Type::SCGC5
__IO uint32_t SCGC5
System Clock Gating Control Register 5, offset: 0x1038.
Definition: MKL25Z4.h:5270
MTB_Type::DEVICECFG
__I uint32_t DEVICECFG
Device Configuration Register, offset: 0xFC8.
Definition: MKL25Z4.h:3231
MTBDWT_Type::DEVICETYPID
__I uint32_t DEVICETYPID
Device Type Identifier Register, offset: 0xFCC.
Definition: MKL25Z4.h:3495
PORTA_IRQn
PORTA Pin detect.
Definition: MKL25Z4.h:174
MCG_Type::C1
__IO uint8_t C1
MCG Control 1 Register, offset: 0x0.
Definition: MKL25Z4.h:2757
LPTMR_Type::CMR
__IO uint32_t CMR
Low Power Timer Compare Register, offset: 0x8.
Definition: MKL25Z4.h:2614
IRQn_Type
IRQn_Type
Definition: ADuCRF101.h:69
UART_Type::BDL
__IO uint8_t BDL
UART Baud Rate Register: Low, offset: 0x1.
Definition: MKL25Z4.h:6523
SIM_Type::UIDML
__I uint32_t UIDML
Unique Identification Register Mid Low, offset: 0x105C.
Definition: MKL25Z4.h:5279
PORT_Type::GPCHR
__O uint32_t GPCHR
Global Pin Control High Register, offset: 0x84.
Definition: MKL25Z4.h:4333
UART0_Type::C5
__IO uint8_t C5
UART Control Register 5, offset: 0xB.
Definition: MKL25Z4.h:6882
USB_Type::OBSERVE
__I uint8_t OBSERVE
USB OTG Observe register, offset: 0x104.
Definition: MKL25Z4.h:7303
ADC_Type::MG
__IO uint32_t MG
ADC Minus-Side Gain Register, offset: 0x30.
Definition: MKL25Z4.h:255
CMP_Type::FPR
__IO uint8_t FPR
CMP Filter Period Register, offset: 0x2.
Definition: MKL25Z4.h:617
ADC_Type::CLM0
__IO uint32_t CLM0
ADC Minus-Side General Calibration Value Register, offset: 0x6C.
Definition: MKL25Z4.h:270
RTC_Type::CR
__IO uint32_t CR
RTC Control Register, offset: 0x10.
Definition: MKL25Z4.h:5027
NV_Type::FPROT2
__I uint8_t FPROT2
Non-volatile P-Flash Protection 1 - High Register, offset: 0x9.
Definition: MKL25Z4.h:3702
TPM_Type::CONF
__IO uint32_t CONF
Configuration, offset: 0x84.
Definition: MKL25Z4.h:6072
LPTMR0_IRQn
LPTMR0 interrupt.
Definition: MKL25Z4.h:172
UART0_Type::C4
__IO uint8_t C4
UART Control Register 4, offset: 0xA.
Definition: MKL25Z4.h:6881
RTC_Type::LR
__IO uint32_t LR
RTC Lock Register, offset: 0x18.
Definition: MKL25Z4.h:5029
DMA_Type::DSR_BCR
__IO uint32_t DSR_BCR
DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10. ...
Definition: MKL25Z4.h:997
CMP_Type::DACCR
__IO uint8_t DACCR
DAC Control Register, offset: 0x4.
Definition: MKL25Z4.h:619
NV_Type::BACKKEY3
__I uint8_t BACKKEY3
Backdoor Comparison Key 3., offset: 0x0.
Definition: MKL25Z4.h:3693
MCG_Type::ATCVH
__IO uint8_t ATCVH
MCG Auto Trim Compare Value High Register, offset: 0xA.
Definition: MKL25Z4.h:2767
MCG_Type
MCG - Register Layout Typedef.
Definition: MKL25Z4.h:2756
FGPIO_Type::PSOR
__O uint32_t PSOR
Port Set Output Register, offset: 0x4.
Definition: MKL25Z4.h:1330
SIM_Type::SCGC4
__IO uint32_t SCGC4
System Clock Gating Control Register 4, offset: 0x1034.
Definition: MKL25Z4.h:5269
SPI0_IRQn
SPI0 single interrupt vector for all sources.
Definition: MKL25Z4.h:154
SIM_Type::SCGC6
__IO uint32_t SCGC6
System Clock Gating Control Register 6, offset: 0x103C.
Definition: MKL25Z4.h:5271
MCG_Type::C4
__IO uint8_t C4
MCG Control 4 Register, offset: 0x3.
Definition: MKL25Z4.h:2760
UART1_IRQn
UART1 status and error.
Definition: MKL25Z4.h:157
USB_Type::OTGSTAT
__IO uint8_t OTGSTAT
OTG Status register, offset: 0x18.
Definition: MKL25Z4.h:7265
TPM_Type::CnV
__IO uint32_t CnV
Channel (n) Value, array offset: 0x10, array step: 0x8.
Definition: MKL25Z4.h:6067
PMC_Type::LVDSC1
__IO uint8_t LVDSC1
Low Voltage Detect Status And Control 1 register, offset: 0x0.
Definition: MKL25Z4.h:4186
ADC_Type::CLMD
__IO uint32_t CLMD
ADC Minus-Side General Calibration Value Register, offset: 0x54.
Definition: MKL25Z4.h:264
ROM_Type::PERIPHID5
__I uint32_t PERIPHID5
Peripheral ID Register, offset: 0xFD4.
Definition: MKL25Z4.h:4841
TSI_Type::DATA
__IO uint32_t DATA
TSI DATA Register, offset: 0x4.
Definition: MKL25Z4.h:6346
SIM_Type::SRVCOP
__O uint32_t SRVCOP
Service COP Register, offset: 0x1104.
Definition: MKL25Z4.h:5283
USB_Type::OTGCTL
__IO uint8_t OTGCTL
OTG Control register, offset: 0x1C.
Definition: MKL25Z4.h:7267
MTB_Type::POSITION
__IO uint32_t POSITION
MTB Position Register, offset: 0x0.
Definition: MKL25Z4.h:3216
DMA1_IRQn
DMA channel 1 transfer complete.
Definition: MKL25Z4.h:145
DAC_Type::C1
__IO uint8_t C1
DAC Control Register 1, offset: 0x22.
Definition: MKL25Z4.h:819
MCG_Type::C5
__IO uint8_t C5
MCG Control 5 Register, offset: 0x4.
Definition: MKL25Z4.h:2761
LLWU_Type
LLWU - Register Layout Typedef.
Definition: MKL25Z4.h:2274
UART_Type::C4
__IO uint8_t C4
UART Control Register 4, offset: 0x8.
Definition: MKL25Z4.h:6530
ADC_Type::SC2
__IO uint32_t SC2
Status and Control Register 2, offset: 0x20.
Definition: MKL25Z4.h:251
SPI_Type::C1
__IO uint8_t C1
SPI control register 1, offset: 0x0.
Definition: MKL25Z4.h:5851
NV_Type::BACKKEY7
__I uint8_t BACKKEY7
Backdoor Comparison Key 7., offset: 0x4.
Definition: MKL25Z4.h:3697
SIM_Type::SOPT5
__IO uint32_t SOPT5
System Options Register 5, offset: 0x1010.
Definition: MKL25Z4.h:5263
GPIO_Type
GPIO - Register Layout Typedef.
Definition: MKL25Z4.h:1784
LLWU_Type::FILT1
__IO uint8_t FILT1
LLWU Pin Filter 1 register, offset: 0x8.
Definition: MKL25Z4.h:2283
NV_Type::BACKKEY1
__I uint8_t BACKKEY1
Backdoor Comparison Key 1., offset: 0x2.
Definition: MKL25Z4.h:3695
USB_Type::TOKEN
__IO uint8_t TOKEN
Token register, offset: 0xA8.
Definition: MKL25Z4.h:7289
PORT_Type::ISFR
__IO uint32_t ISFR
Interrupt Status Flag Register, offset: 0xA0.
Definition: MKL25Z4.h:4335
USB_Type::ISTAT
__IO uint8_t ISTAT
Interrupt Status register, offset: 0x80.
Definition: MKL25Z4.h:7269
FTFA_Type::FCCOB7
__IO uint8_t FCCOB7
Flash Common Command Object Registers, offset: 0x8.
Definition: MKL25Z4.h:1512
I2C_Type::C2
__IO uint8_t C2
I2C Control Register 2, offset: 0x5.
Definition: MKL25Z4.h:1965
DMA3_IRQn
DMA channel 3 transfer complete.
Definition: MKL25Z4.h:147
MTB_Type::TAGCLEAR
__I uint32_t TAGCLEAR
Claim TAG Clear Register, offset: 0xFA4.
Definition: MKL25Z4.h:3224
UART0_Type
UART0 - Register Layout Typedef.
Definition: MKL25Z4.h:6870
FGPIO_Type::PTOR
__O uint32_t PTOR
Port Toggle Output Register, offset: 0xC.
Definition: MKL25Z4.h:1332
LLWU_Type::PE3
__IO uint8_t PE3
LLWU Pin Enable 3 register, offset: 0x2.
Definition: MKL25Z4.h:2277
LLWU_Type::ME
__IO uint8_t ME
LLWU Module Enable register, offset: 0x4.
Definition: MKL25Z4.h:2279
UART0_Type::MA1
__IO uint8_t MA1
UART Match Address Registers 1, offset: 0x8.
Definition: MKL25Z4.h:6879
RCM_Type::SRS1
__I uint8_t SRS1
System Reset Status Register 1, offset: 0x1.
Definition: MKL25Z4.h:4685
DAC_Type::C0
__IO uint8_t C0
DAC Control Register, offset: 0x21.
Definition: MKL25Z4.h:818
ROM_Type::PERIPHID4
__I uint32_t PERIPHID4
Peripheral ID Register, offset: 0xFD0.
Definition: MKL25Z4.h:4840
ADC_Type::CFG2
__IO uint32_t CFG2
ADC Configuration Register 2, offset: 0xC.
Definition: MKL25Z4.h:247
SIM_Type::SCGC7
__IO uint32_t SCGC7
System Clock Gating Control Register 7, offset: 0x1040.
Definition: MKL25Z4.h:5272
MTB_Type::LOCKACCESS
__I uint32_t LOCKACCESS
Lock Access Register, offset: 0xFB0.
Definition: MKL25Z4.h:3226
SIM_Type::FCFG1
__IO uint32_t FCFG1
Flash Configuration Register 1, offset: 0x104C.
Definition: MKL25Z4.h:5275
MTBDWT_Type::TBCTRL
__IO uint32_t TBCTRL
MTB_DWT Trace Buffer Control Register, offset: 0x200.
Definition: MKL25Z4.h:3492
PMC_Type::LVDSC2
__IO uint8_t LVDSC2
Low Voltage Detect Status And Control 2 register, offset: 0x1.
Definition: MKL25Z4.h:4187
MTBDWT_Type::DEVICECFG
__I uint32_t DEVICECFG
Device Configuration Register, offset: 0xFC8.
Definition: MKL25Z4.h:3494
DMA_Type
DMA - Register Layout Typedef.
Definition: MKL25Z4.h:991
RTC_Type::SR
__IO uint32_t SR
RTC Status Register, offset: 0x14.
Definition: MKL25Z4.h:5028
NV_Type::FSEC
__I uint8_t FSEC
Non-volatile Flash Security Register, offset: 0xC.
Definition: MKL25Z4.h:3705
SIM_Type::SDID
__I uint32_t SDID
System Device Identification Register, offset: 0x1024.
Definition: MKL25Z4.h:5267
PORTD_IRQn
PORTD Pin detect.
Definition: MKL25Z4.h:175
PMC_Type::REGSC
__IO uint8_t REGSC
Regulator Status And Control register, offset: 0x2.
Definition: MKL25Z4.h:4188
MTB_Type
MTB - Register Layout Typedef.
Definition: MKL25Z4.h:3215
FTFA_Type::FCCOBA
__IO uint8_t FCCOBA
Flash Common Command Object Registers, offset: 0xD.
Definition: MKL25Z4.h:1517
USB_Type::ADDINFO
__I uint8_t ADDINFO
Peripheral Additional Info register, offset: 0xC.
Definition: MKL25Z4.h:7259
ADC_Type::CLPD
__IO uint32_t CLPD
ADC Plus-Side General Calibration Value Register, offset: 0x34.
Definition: MKL25Z4.h:256
ADC_Type::PG
__IO uint32_t PG
ADC Plus-Side Gain Register, offset: 0x2C.
Definition: MKL25Z4.h:254
PIT_Type::LTMR64L
__I uint32_t LTMR64L
PIT Lower Lifetime Timer Register, offset: 0xE4.
Definition: MKL25Z4.h:4022
FGPIO_Type::PDIR
__I uint32_t PDIR
Port Data Input Register, offset: 0x10.
Definition: MKL25Z4.h:1333
I2C_Type::FLT
__IO uint8_t FLT
I2C Programmable Input Glitch Filter register, offset: 0x6.
Definition: MKL25Z4.h:1966
USB_Type::USBCTRL
__IO uint8_t USBCTRL
USB Control register, offset: 0x100.
Definition: MKL25Z4.h:7301
__O
#define __O
Definition: core_cm0.h:188
NV_Type::BACKKEY4
__I uint8_t BACKKEY4
Backdoor Comparison Key 4., offset: 0x7.
Definition: MKL25Z4.h:3700
USB_Type::CTL
__IO uint8_t CTL
Control register, offset: 0x94.
Definition: MKL25Z4.h:7279
I2C_Type::A2
__IO uint8_t A2
I2C Address Register 2, offset: 0x9.
Definition: MKL25Z4.h:1969
USB_Type::ADDR
__IO uint8_t ADDR
Address register, offset: 0x98.
Definition: MKL25Z4.h:7281
I2C1_IRQn
I2C1 interrupt.
Definition: MKL25Z4.h:153
UART_Type::D
__IO uint8_t D
UART Data Register, offset: 0x7.
Definition: MKL25Z4.h:6529
USB_Type::OTGISTAT
__IO uint8_t OTGISTAT
OTG Interrupt Status register, offset: 0x10.
Definition: MKL25Z4.h:7261
USB_Type::ERRSTAT
__IO uint8_t ERRSTAT
Error Interrupt Status register, offset: 0x88.
Definition: MKL25Z4.h:7273
SPI1_IRQn
SPI1 single interrupt vector for all sources.
Definition: MKL25Z4.h:155
NV_Type::FPROT1
__I uint8_t FPROT1
Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA.
Definition: MKL25Z4.h:3703
MCM_Type::PLASC
__I uint16_t PLASC
Crossbar Switch (AXBS) Slave Configuration, offset: 0x8.
Definition: MKL25Z4.h:3068
ROM_Type::PERIPHID0
__I uint32_t PERIPHID0
Peripheral ID Register, offset: 0xFE0.
Definition: MKL25Z4.h:4844
UART_Type::C2
__IO uint8_t C2
UART Control Register 2, offset: 0x3.
Definition: MKL25Z4.h:6525
TPM_Type
TPM - Register Layout Typedef.
Definition: MKL25Z4.h:6061
NV_Type
NV - Register Layout Typedef.
Definition: MKL25Z4.h:3692
LLWU_Type::FILT2
__IO uint8_t FILT2
LLWU Pin Filter 2 register, offset: 0x9.
Definition: MKL25Z4.h:2284
ADC_Type
ADC - Register Layout Typedef.
Definition: MKL25Z4.h:244
ROM_Type::PERIPHID2
__I uint32_t PERIPHID2
Peripheral ID Register, offset: 0xFE8.
Definition: MKL25Z4.h:4846
ADC_Type::OFS
__IO uint32_t OFS
ADC Offset Correction Register, offset: 0x28.
Definition: MKL25Z4.h:253
USB0_IRQn
USB0 interrupt.
Definition: MKL25Z4.h:168
PIT_Type::CVAL
__I uint32_t CVAL
Current Timer Value Register, array offset: 0x104, array step: 0x10.
Definition: MKL25Z4.h:4026
I2C_Type::D
__IO uint8_t D
I2C Data I/O register, offset: 0x4.
Definition: MKL25Z4.h:1964
RTC_Type::IER
__IO uint32_t IER
RTC Interrupt Enable Register, offset: 0x1C.
Definition: MKL25Z4.h:5030
UART0_Type::C2
__IO uint8_t C2
UART Control Register 2, offset: 0x3.
Definition: MKL25Z4.h:6874
FTFA_Type
FTFA - Register Layout Typedef.
Definition: MKL25Z4.h:1503
USB_Type::USBTRC0
__IO uint8_t USBTRC0
USB Transceiver Control Register 0, offset: 0x10C.
Definition: MKL25Z4.h:7307
FGPIO_Type::PDDR
__IO uint32_t PDDR
Port Data Direction Register, offset: 0x14.
Definition: MKL25Z4.h:1334
I2C_Type::SMB
__IO uint8_t SMB
I2C SMBus Control and Status register, offset: 0x8.
Definition: MKL25Z4.h:1968
USB_Type::OTGICR
__IO uint8_t OTGICR
OTG Interrupt Control Register, offset: 0x14.
Definition: MKL25Z4.h:7263
CMP_Type
CMP - Register Layout Typedef.
Definition: MKL25Z4.h:614
CMP_Type::CR0
__IO uint8_t CR0
CMP Control Register 0, offset: 0x0.
Definition: MKL25Z4.h:615
UART0_Type::MA2
__IO uint8_t MA2
UART Match Address Registers 2, offset: 0x9.
Definition: MKL25Z4.h:6880
USB_Type::CONTROL
__IO uint8_t CONTROL
USB OTG Control register, offset: 0x108.
Definition: MKL25Z4.h:7305
__IO
#define __IO
Definition: core_cm0.h:189
FTFA_Type::FCCOB5
__IO uint8_t FCCOB5
Flash Common Command Object Registers, offset: 0xA.
Definition: MKL25Z4.h:1514
UART0_Type::D
__IO uint8_t D
UART Data Register, offset: 0x7.
Definition: MKL25Z4.h:6878
NV_Type::BACKKEY6
__I uint8_t BACKKEY6
Backdoor Comparison Key 6., offset: 0x5.
Definition: MKL25Z4.h:3698
Reserved45_IRQn
Reserved interrupt.
Definition: MKL25Z4.h:173
UART_Type::BDH
__IO uint8_t BDH
UART Baud Rate Register: High, offset: 0x0.
Definition: MKL25Z4.h:6522
USB_Type::STAT
__I uint8_t STAT
Status register, offset: 0x90.
Definition: MKL25Z4.h:7277
PMC_Type
PMC - Register Layout Typedef.
Definition: MKL25Z4.h:4185
MCG_Type::SC
__IO uint8_t SC
MCG Status and Control Register, offset: 0x8.
Definition: MKL25Z4.h:2765
LPTMR_Type::PSR
__IO uint32_t PSR
Low Power Timer Prescale Register, offset: 0x4.
Definition: MKL25Z4.h:2613
ADC_Type::CLP3
__IO uint32_t CLP3
ADC Plus-Side General Calibration Value Register, offset: 0x40.
Definition: MKL25Z4.h:259
FTFA_Type::FCNFG
__IO uint8_t FCNFG
Flash Configuration Register, offset: 0x1.
Definition: MKL25Z4.h:1505
DMA0_IRQn
DMA channel 0 transfer complete.
Definition: MKL25Z4.h:144
UART0_Type::S1
__IO uint8_t S1
UART Status Register 1, offset: 0x4.
Definition: MKL25Z4.h:6875
SVCall_IRQn
Cortex-M0 SV Call Interrupt.
Definition: MKL25Z4.h:139
USB_Type
USB - Register Layout Typedef.
Definition: MKL25Z4.h:7252
PIT_Type::LDVAL
__IO uint32_t LDVAL
Timer Load Value Register, array offset: 0x100, array step: 0x10.
Definition: MKL25Z4.h:4025
MTB_Type::AUTHSTAT
__I uint32_t AUTHSTAT
Authentication Status Register, offset: 0xFB8.
Definition: MKL25Z4.h:3228
I2C_Type::C1
__IO uint8_t C1
I2C Control Register 1, offset: 0x2.
Definition: MKL25Z4.h:1962
FTFA_Type::FCCOB2
__IO uint8_t FCCOB2
Flash Common Command Object Registers, offset: 0x5.
Definition: MKL25Z4.h:1509
MTBDWT_Type::MASK
__IO uint32_t MASK
MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10.
Definition: MKL25Z4.h:3487
SPI_Type::S
__IO uint8_t S
SPI status register, offset: 0x3.
Definition: MKL25Z4.h:5854
CMP_Type::MUXCR
__IO uint8_t MUXCR
MUX Control Register, offset: 0x5.
Definition: MKL25Z4.h:620
ROM_Type::SYSACCESS
__I uint32_t SYSACCESS
System Access Register, offset: 0xFCC.
Definition: MKL25Z4.h:4839
UART0_Type::C3
__IO uint8_t C3
UART Control Register 3, offset: 0x6.
Definition: MKL25Z4.h:6877
SIM_Type::SOPT2
__IO uint32_t SOPT2
System Options Register 2, offset: 0x1004.
Definition: MKL25Z4.h:5260
FTFA_Type::FCCOB8
__IO uint8_t FCCOB8
Flash Common Command Object Registers, offset: 0xF.
Definition: MKL25Z4.h:1519
FTFA_Type::FPROT0
__IO uint8_t FPROT0
Program Flash Protection Registers, offset: 0x13.
Definition: MKL25Z4.h:1523
TPM_Type::CNT
__IO uint32_t CNT
Counter, offset: 0x4.
Definition: MKL25Z4.h:6063
RTC_Type
RTC - Register Layout Typedef.
Definition: MKL25Z4.h:5022
ADC_Type::CLP1
__IO uint32_t CLP1
ADC Plus-Side General Calibration Value Register, offset: 0x48.
Definition: MKL25Z4.h:261
UART_Type::C3
__IO uint8_t C3
UART Control Register 3, offset: 0x6.
Definition: MKL25Z4.h:6528
RTC_Seconds_IRQn
RTC seconds.
Definition: MKL25Z4.h:165
MTB_Type::LOCKSTAT
__I uint32_t LOCKSTAT
Lock Status Register, offset: 0xFB4.
Definition: MKL25Z4.h:3227
MTB_Type::MODECTRL
__I uint32_t MODECTRL
Integration Mode Control Register, offset: 0xF00.
Definition: MKL25Z4.h:3221
I2C_Type::A1
__IO uint8_t A1
I2C Address Register 1, offset: 0x0.
Definition: MKL25Z4.h:1960
DMA_Type::DSR
__IO uint8_t DSR
DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10.
Definition: MKL25Z4.h:1000
PORT_Type
PORT - Register Layout Typedef.
Definition: MKL25Z4.h:4330
NV_Type::FPROT0
__I uint8_t FPROT0
Non-volatile P-Flash Protection 0 - High Register, offset: 0xB.
Definition: MKL25Z4.h:3704
FGPIO_Type
FGPIO - Register Layout Typedef.
Definition: MKL25Z4.h:1328
USB_Type::INTEN
__IO uint8_t INTEN
Interrupt Enable register, offset: 0x84.
Definition: MKL25Z4.h:7271
MTB_Type::FLOW
__IO uint32_t FLOW
MTB Flow Register, offset: 0x8.
Definition: MKL25Z4.h:3218
SIM_Type
SIM - Register Layout Typedef.
Definition: MKL25Z4.h:5256
ADC_Type::CLM2
__IO uint32_t CLM2
ADC Minus-Side General Calibration Value Register, offset: 0x64.
Definition: MKL25Z4.h:268
ADC_Type::CLP4
__IO uint32_t CLP4
ADC Plus-Side General Calibration Value Register, offset: 0x3C.
Definition: MKL25Z4.h:258
SPI_Type::C2
__IO uint8_t C2
SPI control register 2, offset: 0x1.
Definition: MKL25Z4.h:5852
MTB_Type::TAGSET
__I uint32_t TAGSET
Claim TAG Set Register, offset: 0xFA0.
Definition: MKL25Z4.h:3223
FTFA_Type::FCCOB4
__IO uint8_t FCCOB4
Flash Common Command Object Registers, offset: 0xB.
Definition: MKL25Z4.h:1515
FTFA_Type::FPROT1
__IO uint8_t FPROT1
Program Flash Protection Registers, offset: 0x12.
Definition: MKL25Z4.h:1522
RTC_Type::TAR
__IO uint32_t TAR
RTC Time Alarm Register, offset: 0x8.
Definition: MKL25Z4.h:5025
RTC_Type::TSR
__IO uint32_t TSR
RTC Time Seconds Register, offset: 0x0.
Definition: MKL25Z4.h:5023
RTC_IRQn
RTC alarm.
Definition: MKL25Z4.h:164
FGPIO_Type::PCOR
__O uint32_t PCOR
Port Clear Output Register, offset: 0x8.
Definition: MKL25Z4.h:1331
USB_Type::REV
__I uint8_t REV
Peripheral Revision register, offset: 0x8.
Definition: MKL25Z4.h:7257
TSI_Type::TSHD
__IO uint32_t TSHD
TSI Threshold Register, offset: 0x8.
Definition: MKL25Z4.h:6347
ADC_Type::CLM3
__IO uint32_t CLM3
ADC Minus-Side General Calibration Value Register, offset: 0x60.
Definition: MKL25Z4.h:267
GPIO_Type::PTOR
__O uint32_t PTOR
Port Toggle Output Register, offset: 0xC.
Definition: MKL25Z4.h:1788
MCG_Type::C2
__IO uint8_t C2
MCG Control 2 Register, offset: 0x1.
Definition: MKL25Z4.h:2758
MCG_Type::S
__IO uint8_t S
MCG Status Register, offset: 0x6.
Definition: MKL25Z4.h:2763
TPM_Type::MOD
__IO uint32_t MOD
Modulo, offset: 0x8.
Definition: MKL25Z4.h:6064
TPM2_IRQn
TPM2 single interrupt vector for all sources.
Definition: MKL25Z4.h:163
FTFA_Type::FCCOB1
__IO uint8_t FCCOB1
Flash Common Command Object Registers, offset: 0x6.
Definition: MKL25Z4.h:1510
LLWU_Type::F2
__IO uint8_t F2
LLWU Flag 2 register, offset: 0x6.
Definition: MKL25Z4.h:2281
MTBDWT_Type::COMP
__IO uint32_t COMP
MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10.
Definition: MKL25Z4.h:3486
TPM1_IRQn
TPM1 single interrupt vector for all sources.
Definition: MKL25Z4.h:162
SPI_Type
SPI - Register Layout Typedef.
Definition: MKL25Z4.h:5850
I2C_Type
I2C - Register Layout Typedef.
Definition: MKL25Z4.h:1959
FTFA_Type::FSTAT
__IO uint8_t FSTAT
Flash Status Register, offset: 0x0.
Definition: MKL25Z4.h:1504
MCG_Type::ATCVL
__IO uint8_t ATCVL
MCG Auto Trim Compare Value Low Register, offset: 0xB.
Definition: MKL25Z4.h:2768
LPTMR_Type::CNR
__IO uint32_t CNR
Low Power Timer Counter Register, offset: 0xC.
Definition: MKL25Z4.h:2615
ADC_Type::SC3
__IO uint32_t SC3
Status and Control Register 3, offset: 0x24.
Definition: MKL25Z4.h:252
PIT_Type::TFLG
__IO uint32_t TFLG
Timer Flag Register, array offset: 0x10C, array step: 0x10.
Definition: MKL25Z4.h:4028
OSC_Type
OSC - Register Layout Typedef.
Definition: MKL25Z4.h:3911
LLWU_Type::PE4
__IO uint8_t PE4
LLWU Pin Enable 4 register, offset: 0x3.
Definition: MKL25Z4.h:2278
MTBDWT_Type::CTRL
__I uint32_t CTRL
MTB DWT Control Register, offset: 0x0.
Definition: MKL25Z4.h:3483
MTB_Type::DEVICEARCH
__I uint32_t DEVICEARCH
Device Architecture Register, offset: 0xFBC.
Definition: MKL25Z4.h:3229
ADC_Type::CLM4
__IO uint32_t CLM4
ADC Minus-Side General Calibration Value Register, offset: 0x5C.
Definition: MKL25Z4.h:266
Reserved20_IRQn
Reserved interrupt.
Definition: MKL25Z4.h:148
UART_Type::S1
__I uint8_t S1
UART Status Register 1, offset: 0x4.
Definition: MKL25Z4.h:6526
__I
#define __I
Definition: core_cm0.h:186
I2C_Type::S
__IO uint8_t S
I2C Status register, offset: 0x3.
Definition: MKL25Z4.h:1963
FTFA_Type::FCCOB9
__IO uint8_t FCCOB9
Flash Common Command Object Registers, offset: 0xE.
Definition: MKL25Z4.h:1518
DAC_Type::C2
__IO uint8_t C2
DAC Control Register 2, offset: 0x23.
Definition: MKL25Z4.h:820
SysTick_IRQn
Cortex-M0 System Tick Interrupt.
Definition: MKL25Z4.h:141
SIM_Type::COPC
__IO uint32_t COPC
COP Control Register, offset: 0x1100.
Definition: MKL25Z4.h:5282
FTFA_Type::FCCOB3
__IO uint8_t FCCOB3
Flash Common Command Object Registers, offset: 0x4.
Definition: MKL25Z4.h:1508
RCM_Type::RPFC
__IO uint8_t RPFC
Reset Pin Filter Control register, offset: 0x4.
Definition: MKL25Z4.h:4687
USB_Type::BDTPAGE2
__IO uint8_t BDTPAGE2
BDT Page Register 2, offset: 0xB0.
Definition: MKL25Z4.h:7293
Reserved39_IRQn
Reserved interrupt.
Definition: MKL25Z4.h:167
I2C_Type::SLTH
__IO uint8_t SLTH
I2C SCL Low Timeout Register High, offset: 0xA.
Definition: MKL25Z4.h:1970
DMA_Type::DAR
__IO uint32_t DAR
Destination Address Register, array offset: 0x104, array step: 0x10.
Definition: MKL25Z4.h:995
ADC_Type::CLP0
__IO uint32_t CLP0
ADC Plus-Side General Calibration Value Register, offset: 0x4C.
Definition: MKL25Z4.h:262
TSI_Type::GENCS
__IO uint32_t GENCS
TSI General Control and Status Register, offset: 0x0.
Definition: MKL25Z4.h:6345
CMP_Type::SCR
__IO uint8_t SCR
CMP Status and Control Register, offset: 0x3.
Definition: MKL25Z4.h:618
TPM_Type::SC
__IO uint32_t SC
Status and Control, offset: 0x0.
Definition: MKL25Z4.h:6062
NV_Type::FOPT
__I uint8_t FOPT
Non-volatile Flash Option Register, offset: 0xD.
Definition: MKL25Z4.h:3706
SPI_Type::M
__IO uint8_t M
SPI match register, offset: 0x7.
Definition: MKL25Z4.h:5858
MCG_IRQn
MCG interrupt.
Definition: MKL25Z4.h:171
SIM_Type::FCFG2
__I uint32_t FCFG2
Flash Configuration Register 2, offset: 0x1050.
Definition: MKL25Z4.h:5276
ADC_Type::CLMS
__IO uint32_t CLMS
ADC Minus-Side General Calibration Value Register, offset: 0x58.
Definition: MKL25Z4.h:265
DAC0_IRQn
DAC0 interrupt.
Definition: MKL25Z4.h:169
LLWU_Type::F1
__IO uint8_t F1
LLWU Flag 1 register, offset: 0x5.
Definition: MKL25Z4.h:2280
SMC_Type::PMCTRL
__IO uint8_t PMCTRL
Power Mode Control register, offset: 0x1.
Definition: MKL25Z4.h:5717
FTFA_Type::FOPT
__I uint8_t FOPT
Flash Option Register, offset: 0x3.
Definition: MKL25Z4.h:1507
SIM_Type::SOPT1
__IO uint32_t SOPT1
System Options Register 1, offset: 0x0.
Definition: MKL25Z4.h:5257
MCM_Type::PLACR
__IO uint32_t PLACR
Platform Control Register, offset: 0xC.
Definition: MKL25Z4.h:3070
DAC_Type::DATH
__IO uint8_t DATH
DAC Data High Register, array offset: 0x1, array step: 0x2.
Definition: MKL25Z4.h:814
LLWU_IRQn
Low leakage wakeup Unit.
Definition: MKL25Z4.h:151
FTFA_Type::FCCOB6
__IO uint8_t FCCOB6
Flash Common Command Object Registers, offset: 0x9.
Definition: MKL25Z4.h:1513
SIM_Type::UIDL
__I uint32_t UIDL
Unique Identification Register Low, offset: 0x1060.
Definition: MKL25Z4.h:5280
MTB_Type::DEVICETYPID
__I uint32_t DEVICETYPID
Device Type Identifier Register, offset: 0xFCC.
Definition: MKL25Z4.h:3232
ADC_Type::CLM1
__IO uint32_t CLM1
ADC Minus-Side General Calibration Value Register, offset: 0x68.
Definition: MKL25Z4.h:269
SIM_Type::SOPT1CFG
__IO uint32_t SOPT1CFG
SOPT1 Configuration Register, offset: 0x4.
Definition: MKL25Z4.h:5258
SMC_Type::STOPCTRL
__IO uint8_t STOPCTRL
Stop Control Register, offset: 0x2.
Definition: MKL25Z4.h:5718
PIT_Type::LTMR64H
__I uint32_t LTMR64H
PIT Upper Lifetime Timer Register, offset: 0xE0.
Definition: MKL25Z4.h:4021
USB_Type::SOFTHLD
__IO uint8_t SOFTHLD
SOF Threshold Register, offset: 0xAC.
Definition: MKL25Z4.h:7291
DMA_Type::DCR
__IO uint32_t DCR
DMA Control Register, array offset: 0x10C, array step: 0x10.
Definition: MKL25Z4.h:1003
PIT_IRQn
PIT interrupt.
Definition: MKL25Z4.h:166
DMA2_IRQn
DMA channel 2 transfer complete.
Definition: MKL25Z4.h:146
ROM_Type
ROM - Register Layout Typedef.
Definition: MKL25Z4.h:4835
RCM_Type::SRS0
__I uint8_t SRS0
System Reset Status Register 0, offset: 0x0.
Definition: MKL25Z4.h:4684
ADC_Type::CV1
__IO uint32_t CV1
Compare Value Registers, offset: 0x18.
Definition: MKL25Z4.h:249
ADC_Type::CLPS
__IO uint32_t CLPS
ADC Plus-Side General Calibration Value Register, offset: 0x38.
Definition: MKL25Z4.h:257
DAC_Type::SR
__IO uint8_t SR
DAC Status Register, offset: 0x20.
Definition: MKL25Z4.h:817
FTFA_Type::FPROT3
__IO uint8_t FPROT3
Program Flash Protection Registers, offset: 0x10.
Definition: MKL25Z4.h:1520
USB_Type::ERREN
__IO uint8_t ERREN
Error Interrupt Enable register, offset: 0x8C.
Definition: MKL25Z4.h:7275
UART0_IRQn
UART0 status and error.
Definition: MKL25Z4.h:156
FTFA_Type::FPROT2
__IO uint8_t FPROT2
Program Flash Protection Registers, offset: 0x11.
Definition: MKL25Z4.h:1521
SPI_Type::D
__IO uint8_t D
SPI data register, offset: 0x5.
Definition: MKL25Z4.h:5856
ROM_Type::PERIPHID6
__I uint32_t PERIPHID6
Peripheral ID Register, offset: 0xFD8.
Definition: MKL25Z4.h:4842
FTFA_Type::FSEC
__I uint8_t FSEC
Flash Security Register, offset: 0x2.
Definition: MKL25Z4.h:1506
UART0_Type::C1
__IO uint8_t C1
UART Control Register 1, offset: 0x2.
Definition: MKL25Z4.h:6873
ROM_Type::PERIPHID7
__I uint32_t PERIPHID7
Peripheral ID Register, offset: 0xFDC.
Definition: MKL25Z4.h:4843
ADC0_IRQn
ADC0 interrupt.
Definition: MKL25Z4.h:159
MCG_Type::C6
__IO uint8_t C6
MCG Control 6 Register, offset: 0x5.
Definition: MKL25Z4.h:2762
RTC_Type::TPR
__IO uint32_t TPR
RTC Time Prescaler Register, offset: 0x4.
Definition: MKL25Z4.h:5024
FGPIO_Type::PDOR
__IO uint32_t PDOR
Port Data Output Register, offset: 0x0.
Definition: MKL25Z4.h:1329
I2C0_IRQn
I2C0 interrupt.
Definition: MKL25Z4.h:152
UART0_Type::BDL
__IO uint8_t BDL
UART Baud Rate Register Low, offset: 0x1.
Definition: MKL25Z4.h:6872
RCM_Type::RPFW
__IO uint8_t RPFW
Reset Pin Filter Width register, offset: 0x5.
Definition: MKL25Z4.h:4688
PIT_Type::TCTRL
__IO uint32_t TCTRL
Timer Control Register, array offset: 0x108, array step: 0x10.
Definition: MKL25Z4.h:4027
ROM_Type::PERIPHID1
__I uint32_t PERIPHID1
Peripheral ID Register, offset: 0xFE4.
Definition: MKL25Z4.h:4845
LLWU_Type::PE2
__IO uint8_t PE2
LLWU Pin Enable 2 register, offset: 0x1.
Definition: MKL25Z4.h:2276
USB_Type::FRMNUMH
__IO uint8_t FRMNUMH
Frame Number Register High, offset: 0xA4.
Definition: MKL25Z4.h:7287
TSI_Type
TSI - Register Layout Typedef.
Definition: MKL25Z4.h:6344
I2C_Type::RA
__IO uint8_t RA
I2C Range Address register, offset: 0x7.
Definition: MKL25Z4.h:1967
MCG_Type::C3
__IO uint8_t C3
MCG Control 3 Register, offset: 0x2.
Definition: MKL25Z4.h:2759
UART0_Type::BDH
__IO uint8_t BDH
UART Baud Rate Register High, offset: 0x0.
Definition: MKL25Z4.h:6871
ROM_Type::TABLEMARK
__I uint32_t TABLEMARK
End of Table Marker Register, offset: 0xC.
Definition: MKL25Z4.h:4837
HardFault_IRQn
Cortex-M0 SV Hard Fault Interrupt.
Definition: MKL25Z4.h:138
SMC_Type::PMSTAT
__I uint8_t PMSTAT
Power Mode Status register, offset: 0x3.
Definition: MKL25Z4.h:5719
LPTMR_Type
LPTMR - Register Layout Typedef.
Definition: MKL25Z4.h:2611
CMP_Type::CR1
__IO uint8_t CR1
CMP Control Register 1, offset: 0x1.
Definition: MKL25Z4.h:616
NV_Type::BACKKEY5
__I uint8_t BACKKEY5
Backdoor Comparison Key 5., offset: 0x6.
Definition: MKL25Z4.h:3699
OSC_Type::CR
__IO uint8_t CR
OSC Control Register, offset: 0x0.
Definition: MKL25Z4.h:3912
LPTMR_Type::CSR
__IO uint32_t CSR
Low Power Timer Control Status Register, offset: 0x0.
Definition: MKL25Z4.h:2612
MCG_Type::C7
__I uint8_t C7
MCG Control 7 Register, offset: 0xC.
Definition: MKL25Z4.h:2769
UART_Type::C1
__IO uint8_t C1
UART Control Register 1, offset: 0x2.
Definition: MKL25Z4.h:6524
SMC_Type
SMC - Register Layout Typedef.
Definition: MKL25Z4.h:5715
PIT_Type
PIT - Register Layout Typedef.
Definition: MKL25Z4.h:4018
Generated on Thu Jul 6 2017 20:52:46 for Contiki 3.x by   doxygen 1.8.6